Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs

Abstract

Parameterized Synchronous Dataflow (PSDF)

A Model-Based Schedule Representation for Heterogeneous Mapping of Dataflow Graphs

“…Simulation time for complex dataflow models is often dominated by the computation time of the schedule [21]. For some applications, this overhead can be reduced with well-designed quasi-static schedules, which trade off relatively large amounts of static schedule computations with relatively small amounts of runtime schedule adjustments [10].…”

“…Experimental results with different numbers of application graph iterations (processed blocks of data samples) are given in Table 8(a), and a corresponding chart is shown in Figure 8(b). The experiments are performed using the PSDFSim simulation environment, which can be adapted to implement and experiment with different types of schedules for PSDF graphs [21].…”

“…In a previous study with this RPSK application, we defined a general methodology for mapping PSDF graphs into hardware, and demonstrated synthesis results for the RPSK application using this methodology [21]. Analogous to the dynamic scheduling approach described in Section X-A, this methodology is easy to apply due to its generality, and is also useful as it provides a standard method to realize hardware implementations of PSDF graphs.…”

“…The results reported here are synthesis results only (the design was tested thoroughly but not actually fabricated). Table II shows the improvement in area that is achieved by the streamlined DSG representation compared to the general-purpose PSDF-to-hardware mapping approach of [21]. This improvement is accompanied by a formal, dataflow based representation of schedule logic, which can be retargeted systematically to other types of platforms for rapid prototyping and experimentation with platform-specific implementation trade-offs.…”