Model-based mapping of reconfigurable image registration on FPGA platforms

Abstract

Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

Hardware Acceleration of Image Registration Algorithm on FPGA-based Systems on Chip

“…The system runs at 100MHz and achieves a registration speed of 82fps for 640x480 images, while a floating point Matlab implementation on a 2.4GHz Intel Core 2 Quad required 5 seconds per frame, thus succeeding a 400x speedup. [18] presents an innovative method for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. A rigid image registration application under real-time performance constraints is designed with 74MHz maximum operating frequency.…”

Application-Specific Instruction Set Processors for Video Processing

“…Dataflow is a well known computational model and is widely used for expressing the functionality of digital signal processing (DSP) applications, such as audio and video data stream processing, digital communications, and image processing (e.g., see [2,3,4]). These applications usually require real-time processing capabilities and have critical performance constraints.…”

“…For efficient exploration of implementation trade-offs, designers should be able to rapidly target these kinds of platforms for functional prototyping and validation. For example, Sen et al introduced a structured, dataflow-based design methodology for mapping rigid image registration applications onto FPGA platforms under real-time performance constraints [4]. Shen et al presented a method to derive Pareto points in the design space that provide trade-offs between memory usage and performance based on different scheduling strategies [8].…”

“…In model-based design, application subsystems are represented in terms of functional components that interact through formal models of computation (e.g., see [1]). By exposing and exploiting high level application structure that is often difficult to extract from platform-based design tools, model-based approaches facilitate systematic integration, analysis, synthesis, and optimization that can be used to exploit platform-based tools and devices more effectively.Dataflow is a well known computational model and is widely used for expressing the functionality of digital signal processing (DSP) applications, such as audio and video data stream processing, digital communications, and image processing (e.g., see [2,3,4]). These applications usually require real-time processing capabilities and have critical performance constraints.…”