Hardware Acceleration of Image Registration Algorithm on FPGA-based Systems on Chip

Abstract

Image processing algorithms are dominating contemporary digital systems due to their importance and adoption by a large number of application domains. Despite their significance, their computational requirements often limit their usage, especially in deeply embedded designs. Heterogeneous computing systems offer a promising solution for this performance gap, leading to their ever increasing utilization by designers. This work targets the acceleration of an image registration pipeline on a System-on-Chip (SoC) including both general purpose and re-configurable computing elements. The evaluation of our proposed HW/SW co-designed image registration application on a state-of-the-art FPGA based SoC showcases its ability to outperform software designs leading to orders of performance speedup (up to 67x) against embedded CPUs. CCS CONCEPTS• Computing methodologies → Image processing; • Hardware → Hardware accelerators; Hardware-software codesign.

Faber: A Hardware/SoftWare Toolchain for Image Registration

“…In this configuration, the most employed metrics are cross-correlation, mean square error, and mutual information [1] or its normalized version with nonparametric Parzen windows [14]. As for the optimization [6] Open Full Toolchain SimpleElastix [17] Open Full Toolchain HW GPU [21] Open Full Single Configuration GPU [22] Open Full Single Configuration GPU [24] Open Full Single Configuration GPU [23] Open Full Single Configuration FPGA [7] Closed Full Single Configuration FPGA [19] Closed Full Single Configuration FPGA [27] Closed Full Single Configuration FPGA [10] Open Full Single Configuration Faber (this work) Open Partial Toolchain algorithms, evolutionary strategies [15] and Powell's method [16] are among the most used ones [1]. These components properly combined generate a registration pipeline that can be tailored to various applications.…”

“…At the same time, MATLAB proposes fewer algorithms and allows the user to register via GUI or via custom scripts. Concerning the HW-based solutions, different efforts go towards the acceleration of the similarity metric computation and the transformation function, which are the most compute-intensive parts, being the optimizer mainly a lightweight control task [7], [19]. Shams et al present a GPU-based bitonic sort and count approach for accelerating MI [20], which is then used by Ikeda at al.…”

“…Brunn et al offer the acceleration of the interpolation and metric differentiation for 3D diffeomorphic registration [24], integrated in CLAIRE [26]. On the FPGA side, different approaches focus on accelerating similarity metrics, e.g., correlation [19] and MI [7]. Chakraborty et al accelerated the transformation model estimation to perform a CORDIC-based rigid registration [27].…”

“…It is important to note that, according to the literature [7], [10], [19], the similarity metric is the most time-consuming computation, followed by the transformation, while the optimizer is mainly a control task involving parameters update. Literature profiling of IR algorithms shows that the combination of transformation and similarity metric accounts for 99% of the overall time [19].…”

“…It is important to note that, according to the literature [7], [10], [19], the similarity metric is the most time-consuming computation, followed by the transformation, while the optimizer is mainly a control task involving parameters update. Literature profiling of IR algorithms shows that the combination of transformation and similarity metric accounts for 99% of the overall time [19]. Our profiling analysis shows that this combination accounts for 84% to 99% of the IR procedure, highlighting a minimum of 74% for the similarity metric only, which aligns with literature results.…”