Multichip Packaging Design for VLSI-Based Systems

Bartlett, Charles; Segelken, J.M.; Teneketges, N.

doi:10.1109/tchmt.1987.1134788

Cited by 69 publications

(7 citation statements)

References 3 publications

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“…A factorial design experimental approach was applied to quantitatively assess the influence of immersion time, temperature, and solution pH on incorporation of copper sulfide onto the polyimide. A 2 3 factorial design which included a central point and three levels of each variable was employed. A Box-Behnken 12 design was used as described in Table I.…”

Section: A Preparation Of Copper Sulfide Deposited Polyimide Filmmentioning

confidence: 99%

“…Applications in microelectronics 1 include use as an interlayer dielectric in integrated circuits, intermetal insulators in multichip modules, and thermal-mechanical passivation buffer protection layers. 2,3 Kapton, poly[N,NЈ-(oxydiphenylene)pyromellitimide], is a polyimide with high-temperature resistance, good mechanical properties, high flame resistance, good dimensional stability, and low dielectric constant. 4 The properties of polyimide film can be modified by the incorporation of a variety of inorganic additives.…”

Section: Introductionmentioning

confidence: 99%

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Low-resistance films of polyimides with impregnated copper sulfide

et al. 2001

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Surface modification of polyimides has been used to obtain better interaction with an inorganic material. Copper sulfide incorporation onto the surface of commercial Kapton polyimide showed that treatment with base was necessary for adherence of the copper sulfide to the polymeric matrix. The optimized conditions for composite preparation, obtained by response surface methodology, was pH 1.4 at 80°C for 3.67 h. Using these conditions, we obtained electrical resistance as low as 1.0 ohm for CuS\Kapton composites. These optimized conditions were used to prepare other low-resistance polyimide composites. The resulting composites were analyzed by photoelectron spectroscopy. The presence of S(2p) and Cu(2p) peaks demonstrated the incorporation of copper sulfide onto the polyimide surface. Scanning electron microphotographs and the images from atomic force microscopy showed a homogeneous CuS distribution in all composites.

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Section: A Preparation Of Copper Sulfide Deposited Polyimide Filmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-resistance films of polyimides with impregnated copper sulfide

et al. 2001

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“…The use of HWSI provides the size, weight and power reductions that allow a processor system capable of billions of operations per second to be used in small satellite applications. Recent developments in the area of multichip module packaging have shown that the HWSI technology is well suited to highly complex circuits and provides maximum packing density of VLSI chips [5][6][7].…”

Section: Vlsi Implementationmentioning

confidence: 99%

“…Flip-chip spacing is mainly limited by the accuracy of the robotic assembly tool that aligns the chip to the substrate. Chip-to-chip spacings as low as 0.5 mm are achievable with existing robotic assembly technology and have been demonstrated [5]. In addition to the density advantage, flip-chip bonding has superior electrical performance to conventional attachment techniques.…”

Section: Hwsi Node Designmentioning

confidence: 99%

<title>Miniaturized low-power parallel processor for space applications</title>

et al. 1991

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A miniaturized, low-power parallel processor for space applications is under development by Space OJmputer OJrporation for DARPA's Advanced Space Technology Program. The basic goal of this project is the reduction, by an order of magnitude or more, of on-board processor weight, size and power consumption for space-based sensor systems. Our approach for achieving this goal is to use lowpower VLSI devices which maximize throughput per watt, together with threedimensional hybrid wafer-scale integration and packaging technology. In its prototype version, a l2-node processor will have a peak throughput greater than 1.2 GFLOPS and occupy a volume less than 15 cubic inches. . The basic goal of the SCC-lOO project is the reduction, by an order of magnitude or more, of on-board processor weight, size and power consumption for space-based sensor systems. Such processors must employ parallel architectures with multiple processing elements in order to achieve the high throughputs required (up to tens ofbilIions of operations per second). Our approach for achieving this goal is to use advanced VSLI implementations which maximize throughput per watt, together with three-dimensional hybrid wafer-scale integration (HWSI) packaging technology. Once the size o( the processor is reduced, it is possible to use shielding techniques not practical with larger-volume equipment, thereby reducing or even eliminating the need for high-cost, radiation-hardened components. Figure 1 shows a full-scale model of the prototype version of the SCC-lOO space processor with 12 processing nodes. This processor, which has a peak throughput in excess of 1.2 GFLOPS, occupies a volume of less than 15 cubic inches. If a 300 mil thick radiation shield (not shown) is used to enclose and protect the processor assembly, the volume occupied is 35 cubic inches. PROCESSOR REQUIREMENTSA basic requirement for the space processor is high throughput. Depending on the sensor type, sensor parameters and processing functions performed, this throughput can range from hundreds of millions to billions of arithmetic operations per second [2,3,4]. The only way in which such a wide range of performance objectives can be achieved is by use of a parallel processing architecture with multiple processing elements or "nodes".The second requirement is flexibility. This implies two important characteristics: programmability and modularity. It is essential that the processor be general-purpose rather than special-purpose in nature, with

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“…Because of the short length and direct path from the chip to the substrate, the electrical parasitics are very low. 3 Because the bond can be placed anywhere on the chip surface, area bonding of a great many bonds is possible. As all bonding occurs within the footprint of the chip and only a small court area needs to be left for handling and rework equipment access, chip density on the substrate can be \ery high indeed.…”

Section: Introductionmentioning

confidence: 99%

Techniques for the Inspection of Flip Chip Solder Bonded Devices

Burdett

Lodge

Pedder

1989

Microelectronics International

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After a brief introduction to the advantages and method of construction of flip chip solder bond devices, this paper looks at different techniques that can be used to inspect these devices at various stages in their construction. These techniques include optical, infra‐red, acoustic and electron microscopy, radiograph, electrical and tensile testing. The advantages and limitations of each of the techniques are discussed and an outline inspection schedule is suggested.

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Multichip Packaging Design for VLSI-Based Systems

Cited by 69 publications

References 3 publications

Low-resistance films of polyimides with impregnated copper sulfide

Low-resistance films of polyimides with impregnated copper sulfide

<title>Miniaturized low-power parallel processor for space applications</title>

Techniques for the Inspection of Flip Chip Solder Bonded Devices

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