Multichannel SDRAM controller design for H.264/AVC video decoder

Bonatto, Alexsandro Cristóvão; Soares, André Borin; Susin, Altamiro

doi:10.1109/spl.2011.5782638

Cited by 16 publications

(17 citation statements)

References 6 publications

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“…The considered system is illustrated in Figure 6. Similarly to the multi-channel case study in [19], we derive the client requirements from a combination of the industrial systems in [30], [31] and information about the memory traffic of the decoder application from [32]. However, we assume 720p resolution instead of 1080p and that all memory requests have a fixed size of 128 B to be able to satisfy the requirements with a single memory channel.…”

Section: Case Studymentioning

confidence: 99%

“…The Video Engine (VE) generates traffic by reading the compressed video and reference frames for motion compensation (VE in ), and writing decoder output (VE out ). The motion compensation requires at least 285.1 MB/s to decode the video samples at a resolution of 1280 × 720, 8 bpp, at 25 fps [32]. The bandwidth requirement to output the decoded video image is 34.6 MB/s.…”

Section: Case Studymentioning

confidence: 99%

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An efficient configuration methodology for time-division multiplexed single resources

Åkesson

Minaeva

Šůcha

et al. 2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-Complex contemporary systems contain multiple applications, some which have firm real-time requirements while others do not. These applications are deployed on multi-core platforms with shared resources, such as processors, interconnect, and memories. However, resource sharing causes contention between sharing applications that must be resolved by a resource arbiter. Time-Division Multiplexing (TDM) is a commonly used arbiter, but it is challenging to configure such that the bandwidth and latency requirements of the real-time resource clients are satisfied, while minimizing their total allocation to improve the performance of non-real-time clients.This work addresses this problem by presenting an efficient TDM configuration methodology. The five main contributions are: 1) An analysis to derive a bandwidth and latency guarantee for a TDM schedule with arbitrary slot assignment, 2) A formulation of the TDM configuration problem and a proof that it is NP-hard, 3) An integer-linear programming model that optimally solves the configuration problem by exhaustively evaluating all possible TDM schedule sizes, 4) A heuristic method to choose candidate schedule sizes that substantially reduces computation time with only a slight decrease in efficiency, 5) An experimental evaluation of the methodology that examines its scalability and quantifies the trade-off between computation time and total allocation for the optimal and the heuristic algorithms. The approach is also demonstrated on a case study of a HD video and graphics processing system, where a memory controller is shared by a number of processing elements.

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Section: Case Studymentioning

confidence: 99%

Section: Case Studymentioning

confidence: 99%

An efficient configuration methodology for time-division multiplexed single resources

Åkesson

Minaeva

Šůcha

et al. 2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

View full text Add to dashboard Cite

show abstract

“…It has been observed that for high resolution video process using HDMI Port. The power consumption of Video PHY controller is also increasing [2]. There are several techniques are utilized in order to control or reduce the power consumption of different devices such as; optical transmitter [3], energy efficient laser driver [4], Ethernet [5], filters [6].…”

Section: Introductionmentioning

confidence: 99%

Low Power Design of Video PHY Controller (2.0) for HDMI Protocol Using Unidirectional High Performance IO Standard

Abdullah¹,

Malaysia²

2017

GJECS

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Abstract-The Video PHY controller is an important device that provides the interface between Transceivers and video interfaces. This interface either is HDMI or Displayport. HDMI Video PHY controller are more significantly used because they provide the high speed operation for high resolution graphics. However, when high resolution graphics are executed the power consumption of HDMI Video PHY controller becomes critical and this disturb the regular streaming of video or even in some cases may damage the HDMI Video PHY controller. There are various techniques have been adopted but significantly results in power reduction of HDMI Video PHY controller not been achieved. In this paper, the low power design for HDMI Video PHY controller is achieved using unidirectional IO Standard. It is demonstrated that POD IO Standard consumes less power for LVDCI IO Standard. The IO Standard based HDMI Video PHY controller is verified on high frequencies of 2.0 GHz and 6 GHz for providing the maximum line rate of 6 Gb/s. It is determined that power reduction of 51% is accomplished for HDMI based Video using unidirectional POD IO Standard compared to LVDCI IO Standard for 2 GHz operation. For 6 GHz GHz design of HDMI based Video PHY controller the power reduction of 73% is achieved using POD IO Standard compared to LVDCI IO Standard. The proposed design will be to provide high resolution graphics at low power consumption.

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“…The Video PHY controller offers the processing of high resolution video data. It is reported that the processing of high resolution video consumes high power for operating frequencies of 2.0 GHz to 6.25 GHz [1][2]. There are several techniques are utilized in order to control or reduce the power consumption of different devices such as; optical transmitter [3], energy efficient laser driver [4], Ethernet [5], filters [6].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Video PHY Controller Using Unidirection and Bidirectional IO Standard via 7 Series FPGA

Das¹

2017

GJECS

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Abstract-The Video PHY controller offers an interface between transmitters/receivers and video ports. These video ports are categorized in HDMI or Displayport. HDMI Video PHY controller are mostly used for their high speed operation for high resolution graphics. However, the execution of high resolution graphics consumes more power, this creates a need of designing the low power design for Video PHY controller. In this paper, the performance of Video PHY controller is analyzed by comparing the power consumption of unidirectional and bi-directional IO Standard over 7 series FPGA. It is determined that total on-chip power is reduced for unidirectional IO Standard based Video PHY controller compared to bidirectional IO Standard based Video PHY controller. The most significant achievement of this work is that it is concluded that unidirectional IO Standard based Video PHY controller consume least standby power compared to bidirectional IO Standard based Video PHY controller. It is defined that for 6 GHz operated frequency Video PHY controller, the 32% total on-chip power is reduced using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video PHY controller. It is also demonstrated that 97% device static power i.e. standby mode power consumption is reduced using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video PHY controller. The proposed design will be to provide high resolution video processing at low standby power consumption using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video PHY controller.

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Multichannel SDRAM controller design for H.264/AVC video decoder

Cited by 16 publications

References 6 publications

An efficient configuration methodology for time-division multiplexed single resources

An efficient configuration methodology for time-division multiplexed single resources

Low Power Design of Video PHY Controller (2.0) for HDMI Protocol Using Unidirectional High Performance IO Standard

Performance Analysis of Video PHY Controller Using Unidirection and Bidirectional IO Standard via 7 Series FPGA

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