An efficient configuration methodology for time-division multiplexed single resources

Åkesson, Benny; Minaeva, Anna; Šůcha, Přemysl; Nelson, Andrew T.; Hanzálek, Zdeněk

doi:10.1109/rtas.2015.7108439

Cited by 18 publications

(23 citation statements)

References 30 publications

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“…Feasible window sizes and positions have to be determined for each message on each link. Generating a feasible TDMA schedule is a complex task [1], which cannot be computed efficiently at run time. The technique can therefore not be used for achieving our goal of dynamic runtime management.…”

Section: Timing Analysis On Network-on-chipmentioning

confidence: 99%

Invasive computing for timing-predictable stream processing on MPSoCs

Wildermann

Bäder

Bauer

et al. 2016

It - Information Technology

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Multi-Processor Systems-on-a-Chip (MPSoCs) provide sufficient computing power for many applications in scientific as well as embedded applications. Unfortunately, when real-time requirements need to be guaranteed, applications suffer from the interference with other applications, uncertainty of dynamic workload and state of the hardware. Composable application/architecture design and timing analysis is therefore a must for guaranteeing real-time applications to satisfy their timing requirements independent from dynamic workload. Here, Invasive Computing is used as the key enabler for compositional timing analysis on MPSoCs, as it provides the required isolation of resources allocated to each application. On the basis of this paradigm, this work proposes a hybrid application mapping methodology that combines designtime analysis of application mappings with run-time management. Design space exploration delivers several resource reservation configurations with verified real-time guarantees for individual applications. These timing properties can then be guaranteed at run-time, as long as dynamic resource allocations comply with the offline analyzed resource configurations. This article describes our methodology and presents programming, optimization, analysis, and hardware techniques for enforcing timing predictability. A case study illustrates the timing-predictable management of real-time computer vision applications in dynamic robot system scenarios.

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Section: Timing Analysis On Network-on-chipmentioning

confidence: 99%

Invasive computing for timing-predictable stream processing on MPSoCs

Wildermann

Bäder

Bauer

et al. 2016

It - Information Technology

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“…We assume that the allocation of client c in the arbiter can be described with two new LR parameters, We always assume a predictable arbiter is used within the memory controller, like TDM, round-robin [41] or CCSP [42]. [37] shows how to derive the LR parameters for various popular arbiter types, [42] focuses on CCSP, and [52,53] extensively discuss TDM arbiters in the context of LR servers. For the purpose of this book, we only need to look at the details for TDM arbiters, which is done later in Sect.…”

Section: Front-end Performancementioning

confidence: 99%

Reconfigurable Real-Time Memory Controller Architecture

et al. 2016

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The purpose of this chapter is to set the stage on which the rest of this book plays out. We describe the technology that we work with, in the form of the SDRAM chips that external companies produce for us (and the rest of the world) in Sect. 2.1. Because, the same SDRAM chips are used by everyone, it is not surprising that most memory controllers, i.e., the interfaces that interact with these chips, have at least the same high-level structure, as introduced earlier in Sect. 1.2. For the sake of efficiency, the proverbial wheel tends to be invented only a few times before the interested community settles for a design that works in most cases. Further improvements are driven by the needs of specific application areas and the gradual evolution of the surrounding actors and requirements. This book focuses on the area of mixed timecriticality systems, and uses an existing SDRAM controller template for real-time systems, the pattern-based controller [1], as its starting point. The properties of this controller are introduced in Sect. 2.2.The story continues with a detailed description of our novel reconfigurable memory controller architecture in Sect. 2.3. It partially concerns the introduction of concepts and structures used in the controller, and touches upon some of the real-time aspects that are influenced by its structure and implementation. This controller is the framework on which the other contributions in this book are pinned. The memory patterns we generate in Chap. 3 are stored within this controller. The analysis from Chap. 4 and the trade-offs we describe in Chap. 5 apply to memory controllers that follows the architecture template we describe here, and the conservative open-page policy in Chap. 6 is implemented on a slightly modified version of the same template. The embedded reconfiguration hardware enables the controller to adapt to different use-cases as we describe in Chap. 7.In Sect. 2.4, we derive a worst-case performance model for this memory controller architecture, based on a Latency-rate (LR) server abstraction. This performance model applies to many well known arbiters and can be used in frameworks that enable system-level analysis. We then continue with a discussion on the implementation of a hardware instance on Field Programmable Gate Array (FPGA) in Sect. 2.5, which demonstrates that this memory controller is not only conceptually sound, but really works when it is connected to a real SDRAM module and integrated SDRAMSDRAM is an extremely popular type of memory. DRAMExchange (a market analyst) reports that in February 2015 alone, 2.4 billion 2 gibibit (2 30 ) equivalent units were produced worldwide [3], for a total capacity of 5.16 exabits. This amounts to a production rate of 267 GB/s, 1 a relatively modest "bandwidth" that about 100 combined contemporary SDRAM devices (single chips) could easily deliver in the worst case, as we later show in Chap. 5.SDRAM is volatile and used as temporary data storage, similarly to caches or Static Random-Access Memory (SRAM) memories. It only stores d...

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“…The service latency assumes that the busy period starts just after the last slot allocated to the processor core to maximize the number of interfering slots. A service latency analysis for arbitrary TDM slot distributions is presented in [4].…”

Section: Latency-rate Serversmentioning

confidence: 99%

Certifying execution time in multicores

Rodrigues

Åkesson

Florido

et al. 2015

Science of Computer Programming

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Please cite this article in press as: V. Rodrigues et al., Certifying execution time in multicores, Sci. Comput. Program. (2015), http://dx. Highlights• We present a semantics-based program verification framework for embedded real-time critical systems that uses the worst-case execution time (WCET) as the safety parameter. • The verification mechanism uses the certifying properties of duality theory to check WCET estimates.• The verification is performed on embedded systems that have low computational resources and require highly efficient mechanisms in terms of resource usage. • We propose efficient verification of programs running on multicore architectures based on the Abstract-Carrying Code (ACC) framework.• Experimental results demostrate our claims on verification efficiency for a subset of the Malardalen WCET benchmarks. AbstractThis article presents a semantics-based program verification framework for critical embedded real-time systems using the worst-case execution time (WCET) as the safety parameter. The verification algorithm is designed to run on devices with limited computational resources where efficient resource usage is a requirement. For this purpose, the framework of abstract-carrying code (ACC) is extended with an additional verification mechanism for linear programming (LP) by applying the certifying properties of duality theory to check the optimality of WCET estimates. Further, the WCET verification approach preserves feasibility and scalability when applied to multicore architectural models.The certifying WCET algorithm is targeted to architectural models based on the ARM instruction set and is presented as a particular instantiation of a compositional data-flow framework supported on the theoretic foundations of denotational semantics and abstract interpretation. The data-flow framework has algebraic properties that provide algorithmic transformations to increase verification efficiency, mainly in terms of verification time. The WCET analysis/verification on multicore architectures applies the formalism of latency-rate (LR) servers, and proves its correcteness in the context of abstract interpretation, in order to ease WCET estimation of programs sharing resources.

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An efficient configuration methodology for time-division multiplexed single resources

Cited by 18 publications

References 30 publications

Invasive computing for timing-predictable stream processing on MPSoCs

Invasive computing for timing-predictable stream processing on MPSoCs

Reconfigurable Real-Time Memory Controller Architecture

Certifying execution time in multicores

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