Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

Abstract

To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy (STMR) based on multi-objective optimization and evolvable hardware (EHW) against single-event upsets (SEUs) for circuits implemented on field programmable gate arrays (FPGAs) based on static random access memory (SRAM) is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy (TMR) to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits. The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina (MCNC) benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.

Reliable S-Box Hardware Implementation by Gate-Level Fault Masking Enhancement

“…In the recent years, several researchers (Mahdavi and Mohammadi 2010;Sanchez-Clemente et al 2016;Yao et al 2015;Shojaei and Mahani 2016;Sheikh and El-Maleh 2017;Almukhaizim and Makris 2008;Zhou et al 2014) have employed heuristic optimization approach to enhance the reliability factor of digital combinational circuits. Mahdavi and Mohammadi (2010) utilize a combination of single-pass reliability analysis and a circuit simulation framework in an efficient evolutionary approach to improve the reliability of combinational circuits.…”

“…They also combine the evolutionary approach and the probabilistic approach to produce solution with high quality. Yao et al (2015) have presented a fault-tolerant strategy of selective TMR based on evolvable hardware and a multi-objective evolutionary approach. In their approach, different topologies of a circuit with the same functionality are evolved using EHW.…”

“…Technology advancement which includes complexity enhancement, drastic device shrinking, power supply reduction and high operating frequency increases the fault probability (Nicolaidis 2005). Therefore, many fault-tolerant approaches have been developed from circuit to system level (Gao et al 2015;Li et al 2015;Chen and Bazzi 2017;Koren and Su 1979;Flammini et al 2009;El-Maleh and Oughali 2014;Pagliarini et al 2012;Ban and Naviner 2011;Ansari et al 2016;Mahdavi and Mohammadi 2010;Sanchez-Clemente et al 2016;Yao et al 2015;Shojaei and Mahani 2016;Sheikh and El-Maleh 2017;Almukhaizim and Makris 2008;Zhou et al 2014). The faulttolerant approaches in Koren and Su (1979), Flammini et al (2009), El-Maleh and Oughali (2014), Pagliarini et al (2012), Ban and Naviner (2011), Ansari et al (2016), Mahdavi and Mohammadi (2010), Sanchez-Clemente et al (2016), Yao et al (2015), Shojaei and Mahani (2016), Sheikh and El-Maleh (2017), Almukhaizim and Makris (2008) and Zhou et al (2014) are practical for different levels of abstraction (i.e., from circuit to system levels), but introduced intelligent fault-tolerant approaches in Gao et al (2015), Li et al (2015) and Chen and Bazzi (2017) are only practical in system level.…”

XOR Multiplexing Technique for Nanocomputers

“…Hence, how to build reliable systems out of unreliable components is an inevitable problem. In order to solve this problem, scholars have investigated several redundant fault-tolerant techniques, such as N-tuple modular redundancy (e.g., triple modular redundancy) [9,10] and reconfiguration [11][12][13]. However, these techniques do not yield high fault tolerance for nanocomputers due to the extreme high devices' density and the high percentage of faulty components.…”

State synchronization technique based on present input and healthy state for repairable TMR systems

“…To date, the faulty module's repair is often performed by partial scrubbing [9], dynamic partial reconfiguration [10,14] or evolvable hardware [15,16], etc. But all these approaches can only recover the logic of combinational circuits in the system; they cannot insure the state of sequential circuits of the repaired module is synchronized with those of the other modules.…”