2013 22nd Asian Test Symposium 2013
DOI: 10.1109/ats.2013.47
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Multi-histogram ADC BIST System for ADC Linearity Testing

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Cited by 6 publications
(3 citation statements)
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“…For highprecision devices, these requirements are very challenging. Especially for built-in self-test [10,11,12,13,14,15], due to the limitation of chip area, it is difficult to integrate a high-performance signal generator. Therefore, there is a strong need to develop more efficient and practical testing algorithms.…”
Section: Introductionmentioning
confidence: 99%
“…For highprecision devices, these requirements are very challenging. Especially for built-in self-test [10,11,12,13,14,15], due to the limitation of chip area, it is difficult to integrate a high-performance signal generator. Therefore, there is a strong need to develop more efficient and practical testing algorithms.…”
Section: Introductionmentioning
confidence: 99%
“…As in the process for calculating the offset fault, we can identify six transition points at which the output changes. They are determined by the expressions in (6). The length of each section where the values are "00," "01," and "10" representing the results of sub-histogram are calculated mathematically as shown in (7).…”
Section: Calculation Of Pipeline Stage Faultsmentioning
confidence: 99%
“…This test method can precisely measure test performance through the large code bin width. However, its disadvantages include a long test time and the necessity of large amounts of test data [6,7]. To solve these problems, many reduced-code test methods have been proposed.…”
Section: Introductionmentioning
confidence: 99%