Multi-Channel Receiver Nonlinearity Cancellation Using Channel Speculation Passing Algorithm

Zhao, Haotian; Diaz, Julian Camilo Gomez; Hoyos, Sebastián

doi:10.1109/tcsii.2021.3096852

Cited by 3 publications

(4 citation statements)

References 15 publications

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“…Their combined s parameters matrix (s ch ) filters the transmitted symbols and then feeds them to the two stages TH. In the analytical discussion of the model, the input-output characteristics that reflect the buffers' static distortions were modeled using a Taylor polynomial [8,11,12], which depended on v corr in the second stage. For validation, the actual circuit was used.…”

Section: Linearity Calibration Feedback Loopmentioning

confidence: 99%

“…This solution is normally adopted in the reduction in distortions derived from the interleaved channels mismatches [9,10]. In the literature, the calibration of static distortion is rare [11,12], and no co-simulation nor indepth modeling of AFE components is introduced in the system simulation. The scope of this paper is to find a TI-TH circuit capable of achieving through calibration a receiver THD of the order of 50dB across different PVT conditions to maximize the performance of a PAM-8 receiver (RX).…”

Section: Introductionmentioning

confidence: 99%

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A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and compensate for them by setting the optimal bias voltage. This can also be used to cancel the front-end nonlinear effects. The sampler was verified by implementing it in TSMC 5 nm FinFET, and a calibration system in a Pulse Amplitude Modulation transceiver, detecting and minimizing the nonlinearities, is presented. The optimum voltage biasing of the sampler was obtained by co-simulating the circuit with the linearity calibration loop implemented in Verilog-A. The histogram of the sampled signal at the slicer input is shown before and after the calibration to show the improvement in the sampled eye opening. Moreover, the resulting bias is equal to the one that maximizes the total harmonic distortion in transient simulations with a 1 GHz input signal, obtaining a minimum of 48.5 dB of total harmonic distortion across different PVT conditions.

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Section: Linearity Calibration Feedback Loopmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

“…While many techniques can be found in the literature to reduce the non-linearities introduced by the TI ADC interleaving mismatches [8,9], there are relatively few examples of systems that address the non-linearities of the analog frontend. In [10,11], such systems make use of complex algorithms in the digital domain. This paper proposes a TH circuit with tunable non-linearities and a simple calibration loop that allows maximizing the static linearity of the analog front-end by controlling a bias voltage in the analog domain.…”

Section: Introductionmentioning

confidence: 99%

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

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Multi-Channel Nonlinearity Mitigation Using Machine Learning Algorithms

Zhao

Diaz

Hoyos

2024

IEEE Trans. on Mobile Comput.

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Multi-Channel Receiver Nonlinearity Cancellation Using Channel Speculation Passing Algorithm

Cited by 3 publications

References 15 publications

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Multi-Channel Nonlinearity Mitigation Using Machine Learning Algorithms

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