MRC-Based RNS Reverse Converters for the Four-Moduli Sets $\{2^{n} + 1, 2^{n} - 1, 2^{n}, 2^{2n + 1} - 1\}$ and $ \{2^{n} + 1, 2^{n} - 1, 2^{2n}, 2^{2n + 1} - 1\}$

Sousa, Leonel; Antão, Samuel

doi:10.1109/tcsii.2012.2188456

Cited by 45 publications

(15 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hence, these deviations are related to unaccounted effects in the theoretical analysis. This effect is particularly noticeable due to the place and routing complexity of the narrow pitch 65-nm CMOS technology used here (see [38]). However, the area-overhead of the signed proposed design is much smaller than the traditional signed converter.…”

Section: B Experimental Resultsmentioning

confidence: 99%

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form $\{2^{k}, 2^{P}-1\}$

Zarandi

Molahosseini

Sousa

et al. 2017

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

The application of residue number system (RNS) to digital signal processing lies in the ability to operate on signed numbers. However, the available RNS-to-binary (reverse) converters have been designed for unsigned numbers, which means that they do not produce signed outputs. Usually, some additional circuits are introduced at the output of the reverse converter to map the unsigned generated output into a signed number representation. This paper proposes a novel method to design reverse converters with signed output for a class of RNS moduli sets of composite form {2 k , 2 P − 1}. The structure of the modulo adder used in the last stage of the proposed converters is modified in order to reuse the internal circuits to produce the signed output. This adder component is especially designed for achieving reverse converters with signed output, imposing very low area and delay overheads compared with unsigned converters. The proposed approach is applied to design reverse converters for different moduli sets and to implement application specific integrated circuits. Experimental results show that for a 4-moduli converter, the proposed design can outperform the traditional method to obtain signed outputs by improving the delay, chip-area, and energy consumption by up to 9%, 21%, and 35%, respectively.Index Terms-Computer arithmetic, modulo adder, residue arithmetic, residue number system (RNS), signed reverse converter.

show abstract

Section: B Experimental Resultsmentioning

confidence: 99%

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form $\{2^{k}, 2^{P}-1\}$

Zarandi

Molahosseini

Sousa

et al. 2017

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…5 (similarly as in [29]) to the 2-moduli set {m 1 , m 2 m 3 }, which provides the final result X = {x 1 , X 23 } given by…”

Section: New Basic Functionsmentioning

confidence: 99%

Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels

Patronik

Piestrak

2017

J Sign Process Syst

View full text Add to dashboard Cite

This paper presents a new general approach to simplify residue-to-binary (reverse) converters for a Residue Number System (RNS) composed of an arbitrary set of moduli. It is suggested to formulate the basic equation of the reverse converter in a form consisting of two separate parts: one depending on input variables of the converter whereas the other is a single constant. Then, the constant, instead of being added inside the reverse converter, can be shifted out to the residue datapath channels, in most cases at no hardware cost or extra delay. Thus, the hardware cost of the converter is reduced, because its multi-operand adder has one operand less to handle. To illustrate various design issues of this new design approach and to prove its efficiency, a new design method of the residue-to-binary (reverse) converters for the 3-moduli set {2 n − 1, 2 n , 2 n + 1} is considered. Two versions of the new converters for the 3-moduli set {2 n − 1, 2 n , 2 n + 1} as well as several of their known counterparts were synthesized for all dynamic ranges from 8 to 38 bits (i.e., for 3 ≤ n ≤ 13). The results obtained suggest that, compared to the best of the state-of-the-art converters, at least one of two versions of our converters is superior with respect to area and power consumption, for all dynamic ranges considered, in some cases accompanied by slight delay reduction. The area is reduced from about 5 % to about 20 % and the largest savings are observed for the power consumption-from over 10 % up to 27 %.

show abstract

“…(6) and Eq. (7). For the cases X (1h) and X (2h) , the use of the proposed parameter selection h = B provides an average reduction of 3.5 times in the number of comparisons …”

Section: Parameter Selectionmentioning

confidence: 99%

“…Other RNS with larger DR such as 4n [4], 5n [5], [6], 6n [7], [8], or 8n + 1 [9] still have the limitation of the number of channels, which translates into inefficient arithmetic RNS units for DSP applications with large operands. The use of New CRT-I algorithm has demonstrated to be one of the most efficient solutions for large DRs [2].…”

Section: Introductionmentioning

confidence: 99%

RNS reverse converters based on the new Chinese Remainder Theorem I

Pettenghi

Sousa

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

In the last years, research on residue number systems (RNS) has targeted larger dynamic ranges in order to further explore the inherent parallelism of these systems. In this paper, a performance analysis is presented for RNS-to-binary architectures based on New Chinese Remainder Theorem I (New CRT-I). Four different approaches are explored, each of them focused on the area or delay reduction of one specific stage of the converter. In addition, a selection of the constants associated to these algorithm approaches is proposed, which results into significant area reductions. Experimental results show that the use of an appropriate parameter selection can achieve a reduction of area and delay around 21% in comparison with the best solutions existing in the state-of-the-art using the New CRT-I technique and conventional parameter selection.

show abstract

MRC-Based RNS Reverse Converters for the Four-Moduli Sets $\{2^{n} + 1, 2^{n} - 1, 2^{n}, 2^{2n + 1} - 1\}$ and $ \{2^{n} + 1, 2^{n} - 1, 2^{2n}, 2^{2n + 1} - 1\}$

Cited by 45 publications

References 15 publications

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form $\{2^{k}, 2^{P}-1\}$

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form $\{2^{k}, 2^{P}-1\}$

Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels

RNS reverse converters based on the new Chinese Remainder Theorem I

Contact Info

Product

Resources

About