In this paper, we present a new residue number system (RNS) {2 n − 1, 2 n , 2 n + 1, 2 n+1 + 1, 2 n−1 + 1} of five wellbalanced moduli that are co-prime for odd n. This new RNS complements the 5-moduli RNS system proposed before for even n {2 n − 1, 2 n , 2 n + 1, 2 n+1 − 1, 2 n−1 − 1}. With the new set, we also present a novel approach to designing multimoduli reverse converters that focuses strongly on moving a significant amount of computations off the critical path. The synthesis of the resulting design over the ST Microelectronics 65nm LP library demonstrates that the delay, area, and power characteristics improve the performance and power consumption of the existing complementary 5-moduli set.

Number comparison has long been recognized as one of the most fundamental non-modular arithmetic operations to be executed in a non-positional Residue Number System (RNS). In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on a newly introduced modified diagonal function, whose strictly monotonic properties make it possible to replace the cumbersome operations of finding the remainder of the division by a large and awkward number with significantly simpler computations involving only a power of 2 modulus. Comparators of numbers represented in sample RNSs composed of varying numbers of moduli and offering different dynamic ranges, designed using various methods, were synthesized for the 65 nm technology. The experimental results suggest that the new circuits enjoy a delay reduction ranging from over 11% to over 75% compared to the fastest circuits designed using existing methods. Moreover, it is achieved using less hardware, the reduction of which reaches over 41%, and is accompanied by significantly reduced power-consumption, which in several cases exceeds 100%. Therefore, it seems that the presented method leads to the design of the most efficient current hardware comparators of numbers represented using a general RNS moduli set.

Several approaches to design of fault-secure or/and fault-tolerant digital finite input response (FIR) filters with varying fault coverage and hardware efficiency have been proposed. However, no specific implementations in modern nanometric technologies using error detecting codes like residue codes or parity codes has been reported yet. In this paper, we will study design of fault-secure multipliersaccumulators (MACs) and digital FIR filters protected using residue codes. Several versions of the fault-secure transpose digital FIR filters were synthesized using RC Compiler v. 8.1 for the 65 nm technology. The results obtained leave no doubts that residue codes could be extremely efficient, because hardware overhead for the transpose digital FIR filters with 16-bit operands, protected using residue code mode 3, is below 2%, which is significantly less than by using any other technique reported to date. To note that, unlike claimed in some recent works, should some elementary design rules be applied, the circuits proposed can guarantee the 100% error coverage.

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