Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units

Patronik, Piotr; Piestrak, Stanisław J.

doi:10.1109/tcsi.2017.2669108

Cited by 18 publications

(9 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Using the diminished-1 technique increases the complexity of the devices. In the paper [17] a new hardware-software approach to the design of the arithmetic unit of the processor using RNS is proposed. Modular operations implemented in hardware using moduli of a special forms 2 , ∈ and 2 − 1, ∈ , > 1.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

et al. 2020

View full text Add to dashboard Cite

Section: Introductionmentioning

confidence: 99%

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

et al. 2020

View full text Add to dashboard Cite

“…An excellent summary of other RNS applications for Digital Signal Processing (DSP) systems and analysis of various design issues can be found in [9]. Coprocessors with limited sets of instructions for high-speed and low power consumption executed in RNS have been proposed [10,11]. Besides these well-established applications, many other emerging RNS applications have been surveyed [12].…”

Section: Introductionmentioning

confidence: 99%

RNS Number Comparator Based on a Modified Diagonal Function

et al. 2020

Self Cite

View full text Add to dashboard Cite

Number comparison has long been recognized as one of the most fundamental non-modular arithmetic operations to be executed in a non-positional Residue Number System (RNS). In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on a newly introduced modified diagonal function, whose strictly monotonic properties make it possible to replace the cumbersome operations of finding the remainder of the division by a large and awkward number with significantly simpler computations involving only a power of 2 modulus. Comparators of numbers represented in sample RNSs composed of varying numbers of moduli and offering different dynamic ranges, designed using various methods, were synthesized for the 65 nm technology. The experimental results suggest that the new circuits enjoy a delay reduction ranging from over 11% to over 75% compared to the fastest circuits designed using existing methods. Moreover, it is achieved using less hardware, the reduction of which reaches over 41%, and is accompanied by significantly reduced power-consumption, which in several cases exceeds 100%. Therefore, it seems that the presented method leads to the design of the most efficient current hardware comparators of numbers represented using a general RNS moduli set.

show abstract

“…Recently, a remarkable effort resulted in the efficient hardware implementation of a sign-magnitude comparator for the moduli set {2 n , 2 n − 1, 2 n+1 − 1} [28]. Additionally, an elegant design approach for the enhanced arithmetic unit of an RNS was proposed in [29] based on a shared hardware/software method. The chosen moduli set consists of an even modulus 2 n with remaining moduli of type 2 m − 1.…”

Section: Introductionmentioning

confidence: 99%

“…To achieve this goal, for the first time, a programmable power-of-two scaler is presented for this augmented three-moduli set. By using a variable scaling factor 2 λ , up to half of the dynamic range of a given RNS can be scaled during runtime for the particular case of p = n. The design approach in [29] can be considered as a potential application of the proposed programmable scaler to ensure its reliability. The efficiency of the proposed RNS scaler has a direct impact on the efficiency of various applications, such as that presented in [29].…”

Section: Introductionmentioning

confidence: 99%

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 ⁿ ⁺ ^p , 2 ⁿ − 1, 2 ⁿ ⁺¹ − 1}

2020

View full text Add to dashboard Cite

Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter‐modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well‐known moduli sets {2n − 1, 2n, 2n + 1} and {2n, 2n − 1, 2n+1 − 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic‐friendly moduli set {2n+p, 2n − 1, 2n+1 − 1}. The proposed algorithm yields high speed and energy‐efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed‐radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

show abstract

Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units

Cited by 18 publications

References 35 publications

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

RNS Number Comparator Based on a Modified Diagonal Function

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 ⁿ ⁺ ^p , 2 ⁿ − 1, 2 ⁿ ⁺¹ − 1}

Contact Info

Product

Resources

About

Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units

Cited by 18 publications

References 35 publications

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

RNS Number Comparator Based on a Modified Diagonal Function

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 n + p , 2 n − 1, 2 n +1 − 1}

Contact Info

Product

Resources

About

Efficient programmable power‐of‐two scaler for the three‐moduli set {2 ⁿ ⁺ ^p , 2 ⁿ − 1, 2 ⁿ ⁺¹ − 1}