High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

Lyakhov, Pavel; Valueva, Maria; Valuev, Georgii; Nagornov, Nikolay

doi:10.1109/access.2020.3038496

Cited by 20 publications

(25 citation statements)

References 26 publications

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“…The maximum clock frequency of the proposed device is 31.03% -38.46% higher compared with device based on Winograd method [9] and 1.89% -2.94% higher compared to the filter based on MAC [23] units for the case of 8-and 16-bit devices, but 26.21% less for the case of 8-bit devices. Nevertheless, in comparison with the TMAC-based filter architecture in PNS [13] and in RNS [14] the performance of the proposed device is 7.89% -35.59% lower. The number of LUTs occupied by the proposed device is 18.08% -37.27% less compared with the filter based on Winograd method [9], but 3.83 -7.74 times more compared to other reviewed known architectures.…”

Section: Discussionmentioning

confidence: 84%

“…The proposed architecture of the 8-bit filter has 2.15% lower latency, but 16-and 32-bit devices have 3.42% -52.52% more delay, compared to the known architecture based on TMAC units with computations in RNS. The area of the proposed device is approximately twice the area of a device based on TMAC units with computations in RNS [14]. The main advantage of the proposed filter architecture based on the Winograd method with calculations in RNS with special type modules is to reduce the processing time of a two-dimensional signal.…”

Section: Discussionmentioning

confidence: 99%

“…In addition, parameters of filters consisting of TMAC blocks with calculations in RNS with special type moduli were calculated [14]. For modulo 2 α , the device parameters are calculated by formulas (41), and for modulo 2 α − 1 calculation, the parameters of filter delay and area are follows:…”

Section: A Theoretical Analysismentioning

confidence: 99%

“…The authors of the paper [13] proposed a filter architecture with finite impulse response based on truncated MAC units (TMAC). In [14], the implementation of TMAC units in RNS with moduli of a special type 2 α and 2 α − 1, α ∈ N, where N is the natural numbers set. The moduli of a special type allow you to reduce the operation of calculating the remainder of a division to a bit shift operation (for modulo 2 α ) and an addition operation of α-bit numbers (for modulo 2 α − 1) [15], and use efficient addition and multiplication techniques [16], [17].…”

Section: Introductionmentioning

confidence: 99%

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Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

et al. 2021

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Improving the technical characteristics of digital signal processing devices is an important problem in many practical tasks. The paper proposes the architecture of a device for two-dimensional filtering in a residue number system (RNS) with moduli of a special type according to the Winograd method. The work carried out the technical parameters theoretical analysis of the proposed filter architecture for different RNS moduli sets by the ''unit-gate''-model. In addition, the proposed architecture is compared with known digital filter implementations. The theoretical analysis results showed that the use of the proposed filter architecture makes it possible to increase the signal processing speed by 1.33 -6.90 times, in comparison with the known device implementations. Also, in the work, the hardware simulation of the proposed filter architecture was performed on FPGA, which showed that the performance of the proposed device is 1.31 -4.12 times higher than known digital filter architectures. The research results can be used in digital signal processing systems to increase their performance and reduce hardware costs. In addition, the developed architectures can be applied in the development of hardware accelerators for complex digital signals analysis systems.INDEX TERMS Digital filters, residue number system, Winograd method.

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Section: Discussionmentioning

confidence: 84%

Section: Discussionmentioning

confidence: 99%

Section: A Theoretical Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

et al. 2021

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“…Image filtering implementation method in RNS with replacing the computationally complex division operation by the multiplication and scaling is developed in [62]. A high-performance hardware implementation of digital filtering using truncated multiplyaccumulate units in RNS is presented in [63]. FPGA simulation results show that the proposed RNS-based approach increases the digital filtering speed by about 4 times and reduces the hardware costs by 3 times compared to the binary number system (BNS).…”

Section:  mentioning

confidence: 99%

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

et al. 2022

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Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (fieldprogrammable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.INDEX TERMS Medical image processing, discrete wavelet transform, scaled filter coefficients, residue number system, high-performance computing, hardware accelerator, field-programmable gate arrays.

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Modulo 2k + 1 Truncated Multiply-Accumulate Unit

Bergerman

Lyakhov

Abdulsalyamova

2023

Lecture Notes in Networks and Systems

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High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

Cited by 20 publications

References 26 publications

Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

Modulo 2k + 1 Truncated Multiply-Accumulate Unit

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