Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (fieldprogrammable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.INDEX TERMS Medical image processing, discrete wavelet transform, scaled filter coefficients, residue number system, high-performance computing, hardware accelerator, field-programmable gate arrays.

In this paper, we present a reverse conversion from a two-stage Residue Number System (RNS) to a Binary Number System (BNS) with a special set of level 1 modules {2 α1, 2 α2 − 1, …, 2αn − 1} and level 2 modules {2 β1, 2 β2 − 1, …, 2 β k − 1}. The proposed method is based on the Chinese Remainder Theorem (CRT) with fractions and using a calculation method that uses constant multiplications to speed up calculations. This article discusses the simulation of FPGA reverse conversion to a two-stage RNS using the proposed method and the standard CRT using adders, their comparison of latency and hardware costs.

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