Moving Current Filaments in Integrated DMOS Transistors Under Short-Duration Current Stress

Automated setup for thermal imaging and electrical degradation study of power DMOS devices

“…In the former case the current filaments stay and thermally destroy the device close to the surface. In the latter case the filament moves, with a maximum temperature reached deeper in the bulk at the edge of the buried layer profile [1]. This was observed recently by a 2D transient interferometric mapping (TIM [1,6]) method.…”

“…Electrostatic discharge (ESD) events limit the electrical safe operating area of smart power DMOS devices [1][2][3][4][5] due to the activation of the parasitic bipolar n-p-n transistor, which induces a strongly inhomogeneous current flow. While lateral DMOS devices are destroyed immediately as the bipolar transistor is activated, the vertical DMOS devices may survive in the snapback operation for a certain current interval [1][2][3].…”

“…While lateral DMOS devices are destroyed immediately as the bipolar transistor is activated, the vertical DMOS devices may survive in the snapback operation for a certain current interval [1][2][3]. In the former case the current filaments stay and thermally destroy the device close to the surface.…”

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

“…Also, it is very challenging to make both n-and p-type VDMOS transistors in the same process flow. Therefore, integrated VDMOS transistors are much less common compared to LDMOS devices [13][14][15].…”

“…Most research is for LDMOS transistors, as these devices are much easier to integrate and as such are more common in smart power technologies. Only a few papers exist on reliability assessment of integrated VDMOS transistors [13][14][15]30].…”