MOSFET-like CNFET based logic gate library for low-power application: a comparative study

Abstract

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

Low Leakage Charge Recycling Technique for Power Minimization in Cntfet Circuits

“…Equation 3confirms that I metal does not depend upon the surface-potential change ∆Φ B and it depends only on V ch,DS and T metal . [6] and hence the power gating structure proposed for MOSFET digital circuits can also be extended to carbon nanotubes. As an attempt, the low leakage charge recycling (LLCR) power gating technique shown in Figure 5 is used for minimizing the power dissipation in CNTFET digital circuits.…”

“…Equation (6) reveals that, on the one hand, by increasing the carbon nanotubes, the device on-current can be improved. On the other hand, the power dissipation of circuits gets elevated with the increasing CNTs.…”

“…Power dissipation has become an important reliability issue in the design of submicron level digital devices. Current CMOS technology encounters considerable challenges like short-channel effects, lack of control over leakage and source-to drain tunnelling [1][2][3][4][5][6]. CNTFETs are considered as a promising alternative to the CMOS technology in future nanometre digital design.…”

An Inverter Gate Design Based on Nanoscale S-FED as a Function of Reservoir Thickness

“…The S-FED performance is evaluated in terms of important figures of merit, including transconductance (g m ), gate delay time (τ = CV /I ), energy delay product (EDP) (EDP = CV /I · CV 2 ), and subthreshold slope (SS) [12], [19], [20]. By considering these four metrics, gain, speed, switching energy, and scalability of device can be obtained.…”

Gate dielectric constant engineering for suppression of ambipolar conduction in CNTFETs

“…The SB-CNTFET operates by means of tunnelling. The main disadvantage of this type is that it exhibits strong ambipolar characteristics, resulting in high leakage current at negative gate-to-source voltages (V GS ), which restrict the usage of these devices in CMOS-like logic families [3]. A double-gate structure has been proposed by Pourfath et al [4] as a measure to eliminate this behaviour in SB-CNTFETs.…”