An Inverter Gate Design Based on Nanoscale S-FED as a Function of Reservoir Thickness

Abstract

In this paper, an inverter logic gate has been successfully designed based on the previously proposed sidecontacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates.Index Terms-Inverter, logic gate design, output characteristics, reservoir thickness, side-contacted field-effect diode (S-FED), threshold voltage.

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

“…Physical models include concentration-dependent mobility, lateral electric field-dependent mobility, Fermi statistic dependence, Shockley-Read-Hall and Auger recombination, bandgap narrowing, band-to-band tunneling between the heavily doped S/D layers, and Lombardi continuously variable transmission (CVT) model for expansion components attributed to mobility. Calibration is set up by the simulation of nanoscale S-FED [36,39] using the same physically-based device simulator…”

“…Among the proposed devices, FEDs have the potential to address both above-mentioned device-and circuitassociated bottlenecks through the formation of a PN junction, which is made by utilizing different voltages to Gatedrain (GD) and Gate-source (GS) [36,37]. Due to opposite voltages applied to the drain and GD in the ON state of the FED structure, pinch-off phenomena would not occur; consequently, the drain current does not experience saturation.…”

“…This phenomenon contributes to reducing power dissipation in the S-FED-based circuits. On the other hand, each M-FED used in digital VLSI designs can act as an nMOS or an pMOS; while, a pair of identical S-FEDs with the same geometries can be used in both pull-up and pull-down networks to design robust dynamic logic gates [36,39], memory cells [37,40], multiplexers [41], and electrostatic discharge protection components [42,43]. These CMOS-like configurations not only enjoy enhanced noise margin and reduced power dissipation but also suppress the area overhead taking the same width-to-length ratio into account in all S-FEDs.…”

Improved nanoscale field effect diode

“…Also, the I ON / I OFF ratio of FED is an order of a magnitude larger than a comparable regular MOSFET [2–4]. The FED is an attractive device used to design various digital and analogue circuits such as high‐speed logic gates [4, 5], SRAM and DRAM memory cells [6–11], programmable negative resistance circuit [12], high‐speed comparator [13], variable gain amplifier [14, 15], and electrostatic discharge (ESD) protection circuit [16–18]. As the regular FED cannot work properly at nanoscale length, modified versions of FED are proposed to achieve proper I ON / I OFF ratio at channel lengths below 100 nm [2, 3, 19].…”