Monolithic ultrasound fingerprint sensor

Abstract

This paper presents a 591 × 438-DPI ultrasonic fingerprint sensor. The sensor is based on a piezoelectric micromachined ultrasonic transducer (PMUT) array that is bonded at wafer-level to complementary metal oxide semiconductor (CMOS) signal processing electronics to produce a pulse-echo ultrasonic imager on a chip. To meet the 500-DPI standard for consumer fingerprint sensors, the PMUT pitch was reduced by approximately a factor of two relative to an earlier design. We conducted a systematic design study of the individual PMUT and array to achieve this scaling while maintaining a high fill-factor. The resulting 110 × 56-PMUT array, composed of 30 × 43-μm 2 rectangular PMUTs, achieved a 51.7% fill-factor, three times greater than that of the previous design. Together with the custom CMOS ASIC, the sensor achieves 2 mV kPa − 1 sensitivity, 15 kPa pressure output, 75 μm lateral resolution, and 150 μm axial resolution in a 4.6 mm × 3.2 mm image. To the best of our knowledge, we have demonstrated the first MEMS ultrasonic fingerprint sensor capable of imaging epidermis and sub-surface layer fingerprints. INTRODUCTIONFingerprint sensors capture an electronic image of a human fingerprint through various physical mechanisms, including optical, capacitive, pressure and acoustic mechanisms. Capacitive fingerprint sensors are the standard for identity authentication in numerous applications because of their performance and low cost; the latter is due to the fact that these sensors can be manufactured in a standard integrated circuit manufacturing process. Ultrasonic fingerprint sensors have many advantages over capacitive sensors, including being insensitive to contamination and moisture on the finger. In addition, ultrasonic waves used in pulse-echo imaging can penetrate the finger's epidermis, collecting images of sub-surface features. However, ultrasonic fingerprint sensors previously provided a low resolution or were too difficult to manufacture. With the rapid development of microelectromechanical systems (MEMS) technology, micromachined ultrasonic transducers (MUTs) based on capacitive (CMUT) and piezoelectric (PMUT) transduction have been demonstrated with significantly reduced device sizes for high-resolution applications, low power consumption and better acoustic impedance matching to the medium

Squared PMUT with Enhanced Pressure Sensitivities

“…Knowing the pressure already calibrated from the OPTEL at the same distance, frequency and media, the computed SR is 45.6 mV/MPa and 36.4 mV/MPa in H2O and FC-70 respectively. Considering all the capacitances and applying Equation (1) to correct both inner and outer signals, the final SREOC in H2O and FC-70 would be in the range of 30 V/MPa, which is under our knowledge higher than other reported PMUTs in an array configuration [3,7]. We expect an improved measurement performance, decreasing the influence of the parasitic capacitances through the monolithical integration with the CMOS circuitry, and provide further evidences on this very high sensitivity single PMUT as sensor.…”

Fabrication and Characterization of PZT Fibered-Epitaxial Thin Film on Si for Piezoelectric Micromachined Ultrasound Transducer

“…The neutral axis position ( z NA ) should exist in the elastic plate or underlayer of the piezoelectric thin film normally, which is calculated as [27] $z_{\mathrm{NA}}=\frac{{\sum }_{n=1}^3{t}_n{z}_n{E}_n^{\prime }}{{\sum }_{n=1}^3{t}_n{E}_n^{\prime }}$ where n is the layer index (Si, buffer layer, PZT), z n is the distance between each layer’s middle plane and the bottom of the stack, as shown in Figure 1b. t n is the thickness of each layer.…”

Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays

“…This monolithic integration of a PMUT The integration of PMUTs and CMOS to form a single chip allows for a reduction in parasitic elements, size, weight, and power consumption of the overall system. Recent works [3,[6][7][8] have presented a single-chip ultrasonic fingerprint sensor based on PMUTs that are directly bonded to a CMOS readout application-specific integrated circuit (ASIC) using Al-Ge eutectic bonding. This integration strategy (presented by Reference [8]) is a considerable improvement over the wire bonding method and reduces the electrical parasitic elements, but it is a very expensive process, and due to the presence of special eutectic bonding, the fill factor is affected.…”