2018
DOI: 10.1088/1748-0221/13/01/c01023
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Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

Abstract: The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging proce… Show more

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Cited by 60 publications
(21 citation statements)
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References 7 publications
(6 reference statements)
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“…Promising results of the modified process test chip encouraged the design of two large scale prototypes based on the same technology and front-end, called MALTA [11] and TJ-Monopix [7,12] featuring different readout schemes. The small sensor capacitance yields a very high input signal equal to 15 mV for the Most Probable Value (MPV) ≈ 1500 e − .…”
Section: Tj-monopix Chip Designmentioning
confidence: 99%
“…Promising results of the modified process test chip encouraged the design of two large scale prototypes based on the same technology and front-end, called MALTA [11] and TJ-Monopix [7,12] featuring different readout schemes. The small sensor capacitance yields a very high input signal equal to 15 mV for the Most Probable Value (MPV) ≈ 1500 e − .…”
Section: Tj-monopix Chip Designmentioning
confidence: 99%
“…The MALTA front end with masking and analogue test pulse injection is derived from the ALPIDE front end adapted to the 25 ns timing requirement of ATLAS. Simulations predict a threshold level of 300 e − with a dispersion of 10 e − and an ENC of 10 e − , sufficiently low to avoid the need for an in-pixel threshold adjustment circuit [7]. The pulse height information can be obtained from the time walk between the bunch crossing time and the leading edge of the discriminator signal with a simulated 25 ns in-time threshold of 300 e − .…”
Section: Sensor and Front End Designmentioning
confidence: 99%
“…The chip's matrix architecture is fully clock-less, leading to a low power consumption. Charge deposition information is extracted from the signal's time walk [7]. Pixel sizes are of 36.4 x 36.4 µm 2 , with the sensor being populated with 512 x 512 pixels in total.…”
Section: Sensor Descriptionmentioning
confidence: 99%