2020
DOI: 10.1109/jestpe.2019.2923671
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Monolithic Integration of SiC Power BJT and Small-Signal BJTs for Power ICs

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Cited by 6 publications
(6 citation statements)
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References 29 publications
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“…8 is represented by the simulations, while Fig. 19 presents the results of the measurements and simulations of the case of two paralleled SiC BJTs, where the current mismatch, albeit at smaller value due to the absence of the turn-OFF delay [33], [34], is represented by both the measurements and simulations.…”
Section: Experimental Set-upmentioning
confidence: 99%
“…8 is represented by the simulations, while Fig. 19 presents the results of the measurements and simulations of the case of two paralleled SiC BJTs, where the current mismatch, albeit at smaller value due to the absence of the turn-OFF delay [33], [34], is represented by both the measurements and simulations.…”
Section: Experimental Set-upmentioning
confidence: 99%
“…However, the complexity of the structure and process of HEMT and MOSFET devices leads to degradation of the integrated device performance. 25 In horizontally structured integrated devices, the active region is small and the parasitic effect of metal leads is connected in a series of devices. For vertically structured integrated devices, the growth of p-type and n-type GaN interacts with each other due to the difference in growth temperature, making epitaxial growth of vertically structured devices difficult.…”
Section: Introductionmentioning
confidence: 99%
“…It also provides a cost-effective method and greatly simplifies the fabrication process for monolithic integration. However, the complexity of the structure and process of HEMT and MOSFET devices leads to degradation of the integrated device performance . In horizontally structured integrated devices, the active region is small and the parasitic effect of metal leads is connected in a series of devices.…”
Section: Introductionmentioning
confidence: 99%
“…Modeling RF devices serves a dual purpose: it enhances the success rate of circuit design and facilitates the analysis of electromagnetic compatibility characteristics within the RF system. This process is immensely beneficial for subsequent improvements in system stability [10][11][12][13][14]. The traditional approach to modeling integrated circuits involves testing the chip's internal parameters using a vector network analyzer.…”
Section: Introductionmentioning
confidence: 99%