Monolithic FET structures for high-power control component applications

Maximum powers of low-loss series–shunt FET RF switches

“…Due to low resistance of SRS switch, the signal voltage amplitude V M is close to the voltage across the load and hence across the source-drain region of SHT. The HFET stays in the pinched-off state as long as the input signal amplitude V M 6 2(V G ÀV T ), where V G0 is the gate bias [4]. The maximum switching power of the pinchedoff shunt HFET is given by [2] …”

“…The power limitations in single switching FETs have been analyzed in [4]. In [2] high switching powers achieved with III-Nitride HFETs have been demonstrated and mechanisms limiting the RF power in single HFET have been analyzed.…”

High voltage SOI stacked switch with varying periphery FETs

“…In SOI technology, where the FET breakdown is much lower than the peak RF voltage, stacking FETs into a cascade configuration is a straightforward way to withstand the voltage [3]. It was believed that the voltage across the stack is equally divided among the stacked FETs [4]. For a shunt branch of stacked FETs, the breakdown voltage can thus be written as…”

A D-band SPST switch using parallel-stripline swap with defected ground structure

“…With large resistors R G1 and R G2 floating the gates of transistor T 1 and T 2 at RF, the voltage amplitude of the signal can be effectively increased to 2V th , where V th is the threshold voltage of the nMOS transistor [10,11]. Hence, the input P 1dB of switch with gate biasing resistor is derived in dBm [11] as:…”