Modified Reduced Switch Converter for Grid Interfaced Systems

Mishra, Nidhi; Singh, Bhim

doi:10.1109/ias.2018.8544546

Cited by 5 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, 125 levels are to be obtained using 5 level PUC cells. The value of N is 3 from (6), which shows that only 3 PUC cells are enough to attain 125 levels in the output voltage. It is possible due to the asymmetric selection of voltages within and among the cascaded cells.…”

Section: B Mathematical Modelmentioning

confidence: 99%

See 1 more Smart Citation

Binary-Quintuple Progression Based 12-Switch 25-Level Converter With Nearest Level Modulation Technique for Grid-Tied and Standalone Applications

Mishra

Yadav

Singh

et al. 2021

IEEE Trans. on Ind. Applicat.

Self Cite

View full text Add to dashboard Cite

This paper introduces a cascaded packed U cell (CPUC) multilevel converter (MLC) to achieve a higher-level count in converter voltage with a minimum number of switches. Here, two five-level PUC topologies are connected in a cascaded manner to obtain twenty-five levels in its output converter voltage. The switch count in CPUC is reduced to 12, as compared to the number of semiconductor devices used for obtaining 25 levels in converter output. A binary-quintuple progression is used for selection of voltage ratios between DC voltage sources, and capacitors. CPUC is operated at low-frequency switching, using the nearest level modulation technique (NLMT). The fundamental switching frequency ensures reduced switching losses as compared to pulsewidth modulation (PWM) schemes. The converter performance is analyzed for grid-tied and standalone applications. The performance parameters such as total harmonic distortion (THD) of converter voltage and THD of grid/load current are examined. The CPUC configuration is modeled and simulated in MATLAB/Simulink, and test results are taken using OPAL-RT test bench. The acquired simulation and test results confirm viability, practicability, acceptability, and cost-effectiveness of CPUC-MLI converter over existing MLC topologies for efficient power conversion.

show abstract

Section: B Mathematical Modelmentioning

confidence: 99%

“…Packed U cell (PUC) topology is introduced for achieving reduced switch count. The modified PUC converter with the boost mode is proposed in [6].…”

Section: Introductionmentioning

confidence: 99%

Binary-Quintuple Progression Based 12-Switch 25-Level Converter With Nearest Level Modulation Technique for Grid-Tied and Standalone Applications

Mishra

Yadav

Singh

et al. 2021

IEEE Trans. on Ind. Applicat.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Multilevel inverters (MLI) are gaining much popularity in the research community and industry for applications such as renewable energy source integration [1], and medium and high voltage drives [2] as they produce near-sinusoidal waveforms and exhibit reduced dv/dt and di/dt stresses on the switches. Conventional multilevel structures such as Flying Capacitor (FC), Neutral Point Clamped (NPC), and cascaded H-bridge (CHB) have been widely employed in industry [3], [4].…”

Section: Introductionmentioning

confidence: 99%

11-Level Operation With Voltage-Balance Control of WE-Type Inverter Using Conventional and DE-SHE Techniques

et al. 2021

View full text Add to dashboard Cite

This article presents an 11-level operation of the WE (Wee)-Type inverter. The topology employs a single DC-source, has a reduced number of components, and exhibits a boosting capability. A voltage balancing algorithm is proposed where the inverter's redundant states are employed to maintain the auxiliary DC-link voltage. It is shown that with the control algorithm, the link voltage is preserved at half the primary DC-link voltage, and the 11-level operation is possible for any load. The presented 11-level WEtype structure is also compared with recent 11-level structures and has a lowest cost factor. Two modulation strategies verify the 11-level operation of the inverter: first, a modified nearest level control (MNLC) with the usage of both zero states is developed; and, second, selective harmonic elimination (SHE) is employed, where the angles are generated using a differential evolution (DE) technique. The maximum efficiency of the inverter is 97.55 %. The performance of the inverter is validated in MATLAB/Simulink and on the hardware-in-the-loop platform.INDEX TERMS WE-Type Inverter, 11-level operation, boosted output voltage, modified nearest level control, differential evolution, selective harmonic elimination.

show abstract

“…Multilevel inverter (MLI) and its types are becoming popular in the research and industrial communities for industry applications. They are being considered for integration of renewable energy source [1] and drives [2] due to near to sine waveform generation, and exhibition of lower switch stresses. The increase in the number of levels in the output voltage leads to an increase in the number of capacitors in the conventional Flying Capacitor (FC) inverters, a larger number of clamping diodes in the Neutral Point Clamped (NPC) inverters, and an increment in the DC sources in the Cascaded H-Bridge (CHB) based structures [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Operation of a UXE-Type 11-Level Inverter with Voltage-Balance Modulation Using NLC and ACO-Based SHE

et al. 2021

View full text Add to dashboard Cite

In this article, the UXE-Type inverter is considered for eleven-level operation. This topology exhibits a boosting capability along with reduced switches and one source. An algorithm that utilizes the redundant states to control the voltage-balance of the auxiliary direct current (DC)-link is presented. The proposed control algorithm is capable of maintaining the voltages of each capacitor at Vdc/4 resulting in a successful multilevel operation for all values of load. The inverter is also compared with 11-level inverters. The modulation of the inverter is performed by employing nearest level control and ant colony optimization based selective harmonic elimination. The maximum inverter efficiency is 98.1% and its performance is validated on an hardware-in-the-loop platform.

show abstract

Modified Reduced Switch Converter for Grid Interfaced Systems

Cited by 5 publications

References 12 publications

Binary-Quintuple Progression Based 12-Switch 25-Level Converter With Nearest Level Modulation Technique for Grid-Tied and Standalone Applications

Binary-Quintuple Progression Based 12-Switch 25-Level Converter With Nearest Level Modulation Technique for Grid-Tied and Standalone Applications

11-Level Operation With Voltage-Balance Control of WE-Type Inverter Using Conventional and DE-SHE Techniques

Operation of a UXE-Type 11-Level Inverter with Voltage-Balance Modulation Using NLC and ACO-Based SHE

Contact Info

Product

Resources

About