Moderate kink effect in fully depleted thin-film SOI MOSFETs

Matsumoto, Takuji; Tsuno, M.; Nakabayashi, Hajime; Inoue, Yasuo; Koyanagi, M.

doi:10.1049/el:19950222

Cited by 17 publications

(9 citation statements)

References 3 publications

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“…2(b) for a 10-nm pillar thickness. The moderate breakdown observed at this pillar thickness is well known from studies of planar SOI devices [17]- [19].…”

Section: Discussionsupporting

confidence: 59%

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Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

Hakim

Groot

Gili

et al. 2006

IEEE Trans. Electron Devices

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929is attributed to the absence of gate depletion but of a comparable gate resistance. However, it is important to mention that for device architectures (FinFET, FD-SOI) that require a higher gate work function, the RF performance of deposited metal-gate devices will be reduced. ACKNOWLEDGMENTThe authors would like to thank all the people involved in the 45-nm CMOS Joint Research Program of Philips and Interuniversity MicroElectronics Center. REFERENCES[1] L. Larson, "Silicon technology tradeoffs for radio-frequency/mixed-signal 'systems-on-a-chip'," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 683-699, Mar. 2003 Abstract-A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200-60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias V dc for which the increased drain-current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60-10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate-gate coupling contribute to the drain-current for pillar thicknesses between 100-40 nm.

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“…2(b) for a 10-nm pillar thickness. The moderate breakdown observed at this pillar thickness is well known from studies of planar SOI devices [17]- [19].…”

Section: Discussionsupporting

confidence: 59%

“…The rise in body potential reduces the threshold voltage and forward biases the source-body junction, which can result in parasitic-bipolartransistor (PBT) latch-up. Extensive work has been done on FBEs in both partially depleted (PD) and (FD) planar SOI transistors [16]- [19]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

Hakim

Groot

Gili

et al. 2006

IEEE Trans. Electron Devices

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“…In the body contacted vertical MOSFET potential profile of body is different than that of the vertical MOSFET without body contact due to forced grounding of the body. This difference in current between devices with and without a body contact is also seen in planar devices [21]. For pillar thicknesses of 120 and 80 nm ( fig.…”

Section: Discussionsupporting

confidence: 58%

“…In contrast, the reduction in the normalized breakdown current for pillar thickness < 60 nm is due to the fully depleted regime of operation. The behaviour found for pillar thicknesses < 60 nm, corresponds to the film thickness scaling effect seen in planar SOI MOSFETs [21]. To fully explain the output characteristics in fig.…”

Section: Discussionmentioning

confidence: 84%

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Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

et al. 2016

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Abstract:Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate-gate charge coupling are investigated at pillar thicknesses in the range 200-10 nm. For pillar thickness > 120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses < 60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60-120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behaviour are characterized as a function of pillar thickness and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate-gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation., whereas for pillar thicknesses < 60 nm, the increase in the drain current is found to be governed by the inherent gate-gate charge coupling. Abstract Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate-gate charge coupling are investigated at pillar thicknesses in the range 200-10 nm. For pillar thickness > 120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses < 60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60-120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behaviour are characterized as a function of pillar thickness and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate-gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the...

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Silicon‐On‐Insulator Devices

Balestra

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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The sections in this article are Trends in Microelectronics The SOI Structure SOI Materials Subthreshold Swing and Threshold Voltage of the SOI Mosfet Driving Current Kink Effect Latch and Breakdown Phenomena Self‐Heating Effects Transient Effects Short‐Channel Effects Hot‐Carrier Effects Ultimate Device Architectures Volume Inversion Noise Quantum Effects Influence of Temperature

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Moderate kink effect in fully depleted thin-film SOI MOSFETs

Cited by 17 publications

References 3 publications

Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Silicon‐On‐Insulator Devices

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