Modelling of small MOS devices and device limits

Chatterjee, P.K.; Yang, Boyi; Shichijo, B.E. Hisashi

doi:10.1049/ip-i-1.1983.0023

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…The issue of scaling limits arose in earnest in the early 1980s [4]. At that time, a strong case could be made that pushing minimum geometries below 0.5 micrometers would yield only diminishing returns.…”

Section: The Need For Nanoelectronicsmentioning

confidence: 99%

Nanoelectronics

Bate¹

1990

Nanotechnology

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A summary is given of some research carried out at Texas Instruments over the past few years in the area of quantum semiconductor devices and very small semiconductor structures. The ultimate goal of this work is the creation of a revolutionary digital integrated circuit technology which will permit the downscaling of minimum feature sizes in integrated circuits to continue well into the next century, while maintaining non-cryogenic operation.

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Section: The Need For Nanoelectronicsmentioning

confidence: 99%

Nanoelectronics

Bate¹

1990

Nanotechnology

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“…Based in part upon the failure of depletion isolation, it has been estimated that junction-based switching devices cannot be shrunk appreciably below 0.1 pm. 3 The classical transistor must eventually lose its ubiquity.…”

Section: Transistor Scaling Limitsmentioning

confidence: 99%

Ultrasmall Electronics Architectures

Frazier¹

1988

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Supercomputing with spin-polarized single electrons in a quantum coupled architecture

1994

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We describe a novel quantum technology for possible ultra-fast, ultra-dense and ultra-low-power supercomputing. The technology utilizes single electrons as binary logic devices in which the spin of the~electron encodes the bit information. Both two-dimensional cellular automata and random wired logic can be realized by laying out on a wafer specific geometric patterns of quantum dots each hosting a single electron. Various types of logic gates, combinational circuits for arithmetic logic units, and sequential circuits for memory have been designed. The technology has many advantages such as (1) the absence of physical interconnects between devices (inter-device interaction is provided by quantum mechanical spikspin coupling between single electrons in adjacent quantum dots), (2) ultra-fast switching times of-1 picosecond for individual devices, (3) extremely high bit density approaching 10 terabits c d , (4) non-volatile memory, (5) robustness and possible room-temperature operation with very high noise margin and reliability, (6) a very low power delay product (-J) for switching between logic levels, and (7) a very small power dissipation of a few tens of nanowatts per switching event. In spite of the above advantages, the technology also has some serious drawbacks in that the fan-out of individual logic devices may be small, wiring crossover is very problematic and the devices themselves have no inherent gain so that isolation between input and output is virtually non-existent. These are problems that plague all similar quantum technologies although they are seldom recognized as such. We will discuss these problems, and where possible, offer plausible solutions. In spite of these drawbacks, however, there are still enough attractive features of this technology to merit serious research. In this paper, we will describe how the spin-polarized single-electron logic devices work, along with the associated circuits and architecture. Finally, we will propose a new fabrication technique for realizing these chips which we believe is much more compatible with the demands of the technology than conventional nanofabrication methods.

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Modelling of small MOS devices and device limits

Cited by 6 publications

References 2 publications

Nanoelectronics

Nanoelectronics

Ultrasmall Electronics Architectures

Supercomputing with spin-polarized single electrons in a quantum coupled architecture

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