Modeling the Hysteresis Power Losses of the Output Parasitic Capacitance in Super Junction MOSFETs

Raciti, A.; Rizzo, Santi Agatino; Susinni, Giovanni; Scollo, Rosario; Scuto, Alfio

doi:10.1109/speedam.2018.8445347

Cited by 14 publications

(2 citation statements)

References 23 publications

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“…The Sawyer-Tower technique has traditionally been used for ferroelectric dielectric material characterization [19]; and now has been adapted to characterize large-signal C o of Si, Si-SJ, SiC and GaN power transistors [16]- [18], [20], and very recently of SiC power diodes [15]. It initially obtains the device's output charge characteristic (Q o vs v DS ) by applying a large excitation voltage, and subsequently, C o is obtained by taking the derivative of Q o with respect to v DS .…”

Section: B Measurement Techniques Of Large-signal C O and Q Omentioning

confidence: 99%

“…And discourse on its proper implementation is limited in the technical literature. Recent research on the topic employ the Sawyer-Tower technique [16]- [18], and its variations [13], to demonstrate the difference between large and small-signal C oss curves, however, an indepth explanation of the circuit operation and its limitations is not given. The recent work in [20] addresses some details of the circuit such as the reference capacitor selection and the body-diode operation to a certain extent.…”

Section: B Measurement Techniques Of Large-signal C O and Q Omentioning

confidence: 99%

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Analysis of Large-Signal Output Capacitance of Transistors Using Sawyer–Tower Circuit

Perera

Kampitsis

Erp

et al. 2021

IEEE J. Emerg. Sel. Topics Power Electron.

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A detailed analysis on the Sawyer-Tower method used in the measurement of large-signal output capacitance (Co) of power transistors is presented, followed by important design recommendations to obtain accurate results. Key factors affecting the proper implementation of the technique, such as power amplifier characteristics, load slew-rate, reference capacitor (C ref) and reverse conduction of the device are addressed, with accompanying simulation and experimental results for Si, SiC and GaN devices. A thorough investigation on the selection of C ref is presented, with a new equation to correctly determine its value for a given voltage swing and output capacitance range of the Device Under Test (DUT). We report that the Sawyer-Tower circuit impose the DUT to enter steady-state reverse conduction under certain conditions, leading to charge-voltage (QV) hysteresis patterns unrelated to Co. Our analysis reveals that the origin of this phenomenon is related to DUT's leakage current, and that it could be minimized by proper selection of the excitation frequency. This work intends to provide an effective guide on designing and using the Sawyer-Tower circuit and to induce further scientific insight in characterizing Co.

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