Modeling of substrate current in p-MOSFET's

Ong, T.C.; Ko, P.K.; Hu, Chenming

doi:10.1109/edl.1987.26678

Cited by 26 publications

(8 citation statements)

References 8 publications

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“…Here, was obtained with -dependent , which is smaller than for NMOSFETs of Process A. A reason for is [26] in (6) and (7). It is confirmed that the PMOS DAHC lifetime can be modeled by the same formula as the NMOS DAHC lifetime.…”

Section: A Pmos Dahc Lifetimementioning

confidence: 92%

“…However, the proposed model may have a limitation at or ( eV [26]), where (2), (4), and (5) based on the lucky electron concept may no longer be valid due to EES.…”

Section: B Oxide Structure and A Physical Model For Interface Trap Gmentioning

confidence: 97%

“…From (6) and (7), the hot carrier critical energies for creating damage can be estimated. Assuming eV/cm and eV/cm [26], eV/cm from and 2.7 eV/cm from have been obtained for NMOS and PMOSFETs of Process A, respectively. Similarly, eV/cm from has been obtained for NMOSFETs of Process B.…”

Section: A Critical Carrier Energies For Creating Damagementioning

confidence: 99%

“…Therefore, -dependence of CHE lifetime is caused rather by the exponentially -dependent surface hot electron density than by the potential barrier change. Using eV [26], the values of are estimated at 4.6 eV and 4.0 eV for Process A and Process B, respectively. The values are higher than , where high-energy hot electrons produced by EES play an important role.…”

Section: A Modeling Of Channel Hot Electron Lifetimementioning

confidence: 99%

“…In order to estimate the upper limit of the carrier critical energies, values of the electron and hole mean free paths and are needed. Assuming nm and nm [26], eV and eV have been obtained for NMOSFETs of Process A. The values of and are much lower than the Si-SiO interface potential barrier of 3.1 eV for electrons and 4.5 eV for holes, respectively [27].…”

Section: A Critical Carrier Energies For Creating Damagementioning

confidence: 99%

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A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

Koike

Tatsuuma

2004

IEEE Trans. Device Mater. Relib.

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A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as. The formula is different from the conventional -sub model in that the exponent of is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical -sub model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.

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Section: A Pmos Dahc Lifetimementioning

confidence: 92%

“…However, the proposed model may have a limitation at or ( eV [26]), where (2), (4), and (5) based on the lucky electron concept may no longer be valid due to EES.…”

Section: B Oxide Structure and A Physical Model For Interface Trap Gmentioning

confidence: 97%

Section: A Critical Carrier Energies For Creating Damagementioning

confidence: 99%

Section: A Modeling Of Channel Hot Electron Lifetimementioning

confidence: 99%

Section: A Critical Carrier Energies For Creating Damagementioning

confidence: 99%

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