Modeling of pocket implanted MOSFETs for anomalous analog behavior

Cao, Kanyu; Liu, Weidong; Jin, Xiaodong; Vashanth, K.; Green, K.; Krick, J.; Vrotsos, Tom; Hu, Chenming

doi:10.1109/iedm.1999.823872

Cited by 35 publications

(3 citation statements)

References 3 publications

(3 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The halo-implanted MOS transistor presents undesired effects of reduced output impedance and increased threshold voltage mismatch [9,10]. A smart way to overcome drain halo-implant issues is to use a simple layoutbased approach that does not require any process modification or design rules violations [7].…”

Section: Halo Implants Effectsmentioning

confidence: 99%

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency $$G_m$$ G m -C applications in 130-nm digital CMOS process

Colletta

Ferreira

Pimenta

2014

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents a 0.25-V supplied bulkdriven symmetrical OTA implemented in 130-nm CMOS process. By operating in weak inversion, and using a distributed layout approach, the OTA can benefit from the voltage reduction and high linearity enabled by haloimplanted transistors. The proposed circuit consumes only 10-nW, features a low transconductance of 22-nS, and a total harmonic distortion of 0.53 % for a 100-mV pp input voltage, thus making it suitable for low-frequency and lowpower G m -C applications.

show abstract

Section: Halo Implants Effectsmentioning

confidence: 99%

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency $$G_m$$ G m -C applications in 130-nm digital CMOS process

Colletta

Ferreira

Pimenta

2014

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Apart from DIBL, vertical non uniform doping (VNUD), Drain Induced Threshold Shift (DITS) also change threshold voltage. The compact models for threshold voltage shift were originally developed for BSIM3 and BSIM4 [14]- [16], and had gained popularity and wide acceptance in the device community. BSIM6 makes use of these models, with modification required for charge based formalism [13].…”

Section: B Short Channel Threshold Voltagementioning

confidence: 99%

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

Agarwal

Gupta

Kushwaha

et al. 2015

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.INDEX TERMS BSIM6, MOSFET, SPICE, threshold voltage.

show abstract

“…High-k gate dielectric has become a trend and the impact of short-channel effects (SCEs) has become increasingly significant. Modeling of SCEs has been investigated and published extensively in recent years [2][3][4][5][6][7]. A one-region analytical model for solving the 2D potential distribution in a short-channel MOSFET was published by Nguyen [8].…”

Section: Introductionmentioning

confidence: 99%

A 2D analytical model for SCEs in MOSFETs with high-kgate dielectric

Xie

Ren

et al. 2010

Semicond. Sci. Technol.

View full text Add to dashboard Cite

In this paper, a two-dimensional (2D) analytical potential model for MOSFETs with high-k gate dielectric is derived based on solving a boundary value problem with 2D Poisson's equation. A novel approach to estimate short-channel threshold voltage (V T ) roll-off analytically is also presented and an explicit expression for the short-channel V T roll-off is obtained. Results show that the minimum surface potential along the channel, the inverse slope of subthreshold current, short-channel V T roll-off and drain-induced barrier lowering (DIBL) predicted by the analytical model are in close agreement with 2D numerical simulation (TCAD Sentaurus) without any fitting parameters even down to a sub-20 nm channel length. This model offers a physical insight into short-channel effects and how each of the parameters of a MOSFET quantitatively impacts on V T and other key features of the device. It also serves for compact modeling of high-k gate dielectric MOSFETs.

show abstract

Modeling of pocket implanted MOSFETs for anomalous analog behavior

Cited by 35 publications

References 3 publications

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency $$G_m$$ G m -C applications in 130-nm digital CMOS process

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency $$G_m$$ G m -C applications in 130-nm digital CMOS process

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

A 2D analytical model for SCEs in MOSFETs with high-kgate dielectric

Contact Info

Product

Resources

About