Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

In this endeavour, the fruition of a resurrected tunnel field effect transistor has been investigated incorporating the idea of strained channel engineering along with the implementation of dielectric modulation technique. A non-homogeneous pattern of gate oxide layer is considered with hetero-dielectric architecture at the front gate and linearly graded oxide at the back gate. The buried oxide (BOX) thickness is kept intentionally double that of front oxide one to reduce electric field lines penetrating from drain to source, thus minimising fringing field effect. The surface potential function has been deduced with the help of 2D Poisson's equation assuming appropriate boundary conditions. Lateral electric field and hence total electric field have been computed from channel potential to study tunnelling efficiency, hot carrier effect and drain induced barrier lowering for the aimed device. Finally drain current has been derived with the help of Kane's model upon integration of band-to-band tunnelling rate and the results have been compared with previously published reports to corroborate the eminence of the proposed model. All analytical corollaries are in adroit amity with Silvaco ATLAS simulated data for avowal of the developed modelin terms of sublime short channel behaviour.

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“…The impact of HD divides the channel into four regions [19]. Region I: Due to Permittivity of HfO 2 (ɛ a ) only.…”

Section: Surface Potential Expressionmentioning

confidence: 99%

“…Similarly, at drain end, i.e. y = L ( L 1 + L 2 )

\begin{matrix} right leftthickmathspace.5em \\ ψ_{f 4} (L) & = Q_{1} {normale}^{η_{4} (\frac{L_{2}}{2})} + Q_{2} {normale}^{- η_{4} (\frac{L_{2}}{2})} + Q_{3} \\ = V_{bin} + V_{DS} \\ such that V_{bin} & = V_{T} \log \frac{N_{d}}{n_{i}} + normalΔ V_{b i, s - Si} . \end{matrix}

ε_{h} = ε_{a} + ε_{b}

is the effective permittivity due to SiO 2 and HfO 2 from channel length L 1 /2 up to L 1 + L 2 /2 [19],…”

Section: Analytical Modelingmentioning

confidence: 99%

Analytical modelling of dielectric engineered strained dual‐material double‐gate‐tunnelling field effect transistor

Dash

Saha

Sarkar

2019

IET Circuits, Devices & Systems

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“…The extrinsic capacitances excluding intrinsic capacitances are related to the fringing field effects between the gate electrode and the channel [18,19], having two main components: (i) external fringing electric field and (ii) internal fringing electric field. The external fringing capacitance (C fext ) is bias-independent, whereas the internal fringing capacitance (C fint ) is bias dependent due to the charge variation in the channel close to source or drain.…”

Section: Analogue/rf Performancementioning

confidence: 99%

“…10 and 11 a , b show the plots of gate‐to‐source capacitance ( C gs ) and gate‐to‐drain capacitance ( C gd ) as a function of V gs , which are extracted from small signal AC analysis performed at a frequency of 1 MHz. The total (intrinsic + extrinsic) C gs and C gd capacitances without considering overlap capacitances can be calculated as

C_{normalgs} = C_{normalgsi} + C_{normalfext} + C_{normalfint} normalevaluated normalat false(V_{normalDS} = 0 false)

C_{normalgd} = C_{normalgdi} + C_{normalfext} + C_{normalfint}

The extrinsic capacitances excluding intrinsic capacitances are related to the fringing field effects between the gate electrode and the channel [18, 19], having two main components: (i) external fringing electric field and (ii) internal fringing electric field. The external fringing capacitance ( C fext ) is bias‐independent, whereas the internal fringing capacitance ( C fint ) is bias dependent due to the charge variation in the channel close to source or drain.…”

Section: Analogue/rf Performancementioning

confidence: 99%

“…With short‐gate architecture, the gate‐to‐drain underlap reduces the electric field at channel–drain junction and also, it reduces gate‐to‐drain parasitic capacitance as the gate moves away from the drain [16, 17]. The impact of hetero‐gate dielectric on the performance of TFET has been investigated as a remedy for high gate‐to‐drain capacitance, thus, improving the RF performance of the device [18, 19].…”

Section: Introductionmentioning

confidence: 99%

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DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor

Shylendra¹,

Sharma²,

Kumar³

et al. 2016

Micro & Nano Letters

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The electrostatic behaviour of the different configurations of n-type heterojunction double-gate tunnel field-effect transistor (HDGTFET) has been analysed. The analysis is based on the basics of the circuit elements such as drain current, transconductance, parasitic capacitances, cutoff frequency and gain bandwidth product. From the investigation carried out, it can be inferred that dual metal hetero-dielectric double-gate HDGTFET with gate underlap achieves both low standby power OFF state current and high performance at low supply voltage. The performance of the device having different configurations has been analysed for drain region having a uniform and Gaussian doping profile.

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DC Performance Analysis of Heterojunction Tunnel FET by Optimizing Various High-κ Materials: HfO2/ZrO2 with Low/High-κ Spacer

Dutta¹,

Guha²,

Rahaman³

et al. 2020

Learning and Analytics in Intelligent Systems

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Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

Cited by 41 publications

References 24 publications

Analytical modelling of dielectric engineered strained dual‐material double‐gate‐tunnelling field effect transistor

Analytical modelling of dielectric engineered strained dual‐material double‐gate‐tunnelling field effect transistor

DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor

DC Performance Analysis of Heterojunction Tunnel FET by Optimizing Various High-κ Materials: HfO2/ZrO2 with Low/High-κ Spacer

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