Modeling and synthesis of quality-energy optimal approximate adders

Abstract

Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. We identify a fundamental trade-off between error frequency and error magnitude in a timing-starved adder. We introduce a formal model to prove that for signal processing applications using a quadratic signal-to-noise ratio error measure, reducing bit-wise error frequency is sub-optimal. Instead, energy-optimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns, this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internal-carry structure for higher significance bits.We further demonstrate that remaining approximation error is reduced by realization of conditional bounding (CB) logic for lower significance bits. A key contribution is the formalization of an approximate CB logic synthesis problem that produces a rich space of Pareto-optimal adders with a range of quality-energy tradeoffs. We show how CB logic can be customized to result in overand under-estimating approximate adders, and how a dithering adder that mixes them produces zero-centered error distributions, and, in accumulation, a reduced-variance error. We demonstrate synthesized approximate adders with energy up to 60% smaller than that of a conventional timing-starved adder, where a 30% reduction is due to the superior synthesis of inexact CB logic. When used in a larger system implementing an image-processing algorithm, energy savings of 40% are possible.

Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System

“…Basically, adders have been commonly considered for the approximate implementation as one of the important components in the circuit design. Some of the approximate adder has been discussed in [12] [9] [14]. These works focused on the subcomponent designs, however, the impact of the approximations on structural implementations has not been considered.…”

ApproxIt: An approximate computing framework for iterative methods

“…Various approximate designs for specific arithmetic components were presented in the literature (e.g., [11][12][13][14]), taking advantage of the structural properties of these components. In addition, there are also a few attempts to systematically evaluate and/or generate approximate circuits [15][16][17].…”

Statistical analysis and modeling for error composition in approximate computation circuits

“…Venkataramani et al [27] work with existing commercial synthesis tools and simplify logic based on approximate don't-care (ADC) information under a given error significance bound. Miao et al [21] focus on a methodology to design more efficient adders by combining logic components to reduce the maximum error. In [23], Shin et al provide a heuristic to search for useful approximations based on a truth table to study the tradeoff between the error rate and literal terms (hardware cost).…”