Modeling and sizing for minimum energy operation in subthreshold circuits

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

“…To validate the efficiency of the proposed architecture, we have designed two 9-tap filters; one is based on the proposed architecture (Fig.5), and is denoted as Design 1 and the other denoted as Design 2 based on the transverse structure with multipliers ( Fig.1) which has also been employed in recently reported subthreshold filters [3]. Both designs were simulated using hspice with realistic transistor models from [8].…”

“…In [3], [5] and [7] the authors have reported how such functions can be implemented using subthreshold designs. A standard FIR realization often employed in subthreshold designs is the transversal structure depicted in Fig.1.…”

“…The subthreshold FFT design in [2] showed that the circuit can operate down to V dd = 180mV with very low operating frequency of 64Hz, but the minimum energy point voltage is much higher than this minimal voltage and is reported at 350mV having operational frequency of 10kHz. Transistor sizing that affects the energy consumption and the minimum energy point voltage is considered in the FIR design in [3]. The minimum energy point analysis through an analytical model for the delay and energy of an inverter chain in subthreshold circuits is discussed in [4].…”

“…One key application in wireless sensor nodes with limited energy supply is filtering and therefore the design of filter function has been considered in the recently reported subthreshold designs including [3] and [5]. In this paper we propose a subthreshold FIR architecture which brings the benefits of reduced leakage energy, reduced minimum energy point, reduced operating voltage and increased performance when compared with recently reported subthreshold designs.…”

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

“…It has already been shown that by proper biasing of CMOS logic circuits in subthreshold regime, it is possible to achieve a very low power consumption [7]- [10]. However, supply dependence of the maximum speed of operation (f op ) and power consumption (P diss ) of the CMOS logic circuits have made such circuits very sensitive to the supply voltage variations.…”