Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM Compatible Process

Bergeret, Emmanuel; Gaubert, J.; Pannier, P.; Gaultier, J.M.

doi:10.1109/tcsii.2007.902222

Cited by 42 publications

(38 citation statements)

References 11 publications

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“…In the RFID system, the patch antenna is preferred for use in a reader (BIN), while the dipole antenna [22] is commonly adopted in a transponder (BAN). Therefore, the charge pump circuit should be integrated in the rectifier to pump the voltage from 0.36 V to near 1 V in the worst case [24], [25]. For the implantable wireless communication system, the clock can be directly extracted from the RF input signal with carrier frequency of 2 MHz [10].…”

Section: Rfid Integratationmentioning

confidence: 99%

Integrated successive approximation register analog-to-digital converter for healthcare systems applications

Lai

Huang

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. The proposed a 1-V 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying SAR control logic that reduces half comparator and digital circuit power consumption, the provided SAR ADC achieves low power consumption. Measured results show that at the supply voltage of 1.0 V and sampling rate of 2 MS/s, the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 49.8 dB, a signal-to-noise and distortion ratio (SNDR) of 44.8 dB, an effective number of bits (ENOB) of 7.15 bits, a differential nonlinearity (DNL) of 0.39 LSB, an integral nonlinearity (INL) of 1.6 LSB and a power consumption of 40.2 µW.

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Section: Rfid Integratationmentioning

confidence: 99%

Integrated successive approximation register analog-to-digital converter for healthcare systems applications

Lai

Huang

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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“…The chosen capacitors for this circuit are of through-hole type, which make it easier to modify for optimization, where in [8] the optimization was accomplished at the input impedance of the CMOS chip for a three stage voltage multiplier. The circuit design in this paper uses a capacitor across the load to store and provide DC leveling of the output voltage and its value only affects the speed of the transient response.…”

Section: Seven Stage Voltage Multipliermentioning

confidence: 99%

Optimization of the Voltage Doubler Stages in an RF-DC Convertor Module for Energy Harvesting

Devi¹,

Din²,

Chakrabarty³

2012

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This paper presents an optimization of the voltage doubler stages in an energy conversion module for Radio Frequency (RF) energy harvesting system at 900 MHz band. The function of the energy conversion module is to convert the (RF) signals into direct-current (DC) voltage at the given frequency band to power the low power devices/circuits. The design is based on the Villard voltage doubler circuit. A 7 stage Schottky diode voltage doubler circuit is designed, modeled, simulated, fabricated and tested in this work. Multisim was used for the modeling and simulation work. Simulation and measurement were carried out for various input power levels at the specified frequency band. For an equivalent incident signal of -40 dBm, the circuit can produce 3 mV across a 100 kΩ load. The results also show that there is a multiplication factor of 22 at 0 dBm and produces DC output voltage of 5.0 V in measurement. This voltage can be used to power low power sensors in sensor networks ultimately in place of batteries.

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“…performance [3,4], i.e. sensitivity and input impedance (allowing for increased read ranges and operation bandwidth), as well as the antenna performance [5], have been significant.…”

Section: Introductionmentioning

confidence: 99%

Compact design of UHF RFID and NFC antennas for mobile phones

Paredes¹,

Cairó²,

Zuffanelli³

et al. 2017

IET Microwaves, Antennas & Propagation

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Abstract:A small size and low profile antenna has been developed in order to provide any mobile phone with UHF RFID reader functionality. For that purpose, a patch antenna topology has been chosen on account of the mobile phone battery, which exhibits an electromagnetic behavior similar to a metal plane. The low profile patch antenna has been designed to operate at the European UHF RFID band. In order to communicate the mobile phone with the RFID reader module, NFC technology has been considered. Thus, an NFC antenna, based on square coils, operating at 13.56 MHz has been also designed. Such antenna has been etched on the opposite side of the patch antenna. Overall dimensions of the prototype are 60 mm  100 mm, i.e., small enough to fit the dimensions of a mobile phone. As proof of concepts to evaluate the performance of the designed antennas, an UHF RFID reader module and a NFC reader module are tested. The measured read range reaches up to 1 m for some commercial tags.

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Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM Compatible Process

Cited by 42 publications

References 11 publications

Integrated successive approximation register analog-to-digital converter for healthcare systems applications

Integrated successive approximation register analog-to-digital converter for healthcare systems applications

Optimization of the Voltage Doubler Stages in an RF-DC Convertor Module for Energy Harvesting

Compact design of UHF RFID and NFC antennas for mobile phones

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