Modeling and Analysis of High-Speed I/O Links

Balamurugan, Ganesh; Casper, Bryan; Jaussi, James; Mansuri, M.; O'Mahony, Frank; Kennedy, J.

doi:10.1109/tadvp.2008.2011366

Cited by 69 publications

(36 citation statements)

References 14 publications

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“…(2) shows that the accuracy of both sample mean and variance estimators depend on Ni. As Ni approaches infinity, the error converges to 0.…”

Section: Low Confidence Under Small Sample Sizementioning

confidence: 98%

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Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Chiprout

2013

Proceedings of the 50th Annual Design Automation Conference

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A critical problem in pre-Silicon and post-Silicon validation of analog/mixed-signal circuits is to estimate the distribution of circuit performances, from which the probability of failure and parametric yield can be estimated at all circuit configurations and corners. With extremely small sample size, traditional estimators are only capable of achieving a very low confidence level, leading to either over-validation or under-validation. In this paper, we propose a multipopulation moment estimation method that significantly improves estimation accuracy under small sample size. In fact, the proposed estimator is theoretically guaranteed to outperform usual moment estimators. The key idea is to exploit the fact that simulation and measurement data collected under different circuit configurations and corners can be correlated, and are conditionally independent. We exploit such correlation among different populations by employing a Bayesian framework, i.e., by learning a prior distribution and applying maximum a posteriori estimation using the prior. We apply the proposed method to several datasets including post-silicon measurements of a commercial highspeed I/O link, and demonstrate an average error reduction of up to 2×, which can be equivalently translated to significant reduction of validation time and cost.

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“…(2) shows that the accuracy of both sample mean and variance estimators depend on Ni. As Ni approaches infinity, the error converges to 0.…”

Section: Low Confidence Under Small Sample Sizementioning

confidence: 98%

“…However, in practice, simulation and measurement are both time and cost consuming [2,3,4]. For example, postlayout simulation can be slow, especially for circuits such as SRAM/PLL where extremely small time steps are required for high accuracy.…”

Section: Introductionmentioning

confidence: 99%

Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Chiprout

2013

Proceedings of the 50th Annual Design Automation Conference

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“…The ''thru'' and crosstalk channels are assumed as linear timeinvariant (LTI) [4] and the received signal y k is described in the PAM-2 and PAM-4 case as,…”

Section: Statistical Ber Modelingmentioning

confidence: 99%

“…Under this low BER requirement, empirical analysis is impractical due to current hardware performance limitations. However, simple worst-case analysis techniques, such as peak-distortion analysis, yield highly pessimistic performance estimations which map to inefficient designs that consume excessive power and chip area [4]. This has lead to the development of statistical analysis methods [4,5], which utilize the statistical properties of noise and distortion to rapidly estimate link performance and trade-offs in equalization complexity and modulation format.…”

Section: Introductionmentioning

confidence: 99%

A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter

Min

Lee

Palermo

2012

Microelectronics Journal

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“…Recently, a statistical simulation approach has been used to predict the link BER performance [2]- [6]. So far, the method has been focused on modeling of the data channel since the method has been extensively used for SERDES applications where a clock-data recovery circuit (CDR) is used instead of an explicit clock signal * .…”

Section: Introductionmentioning

confidence: 99%

Clock jitter modeling in statistical link simulation

Chang

2009

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems

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Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling of data channels and the impact of a clock channel is often ignored or primitively approximated using a simple receiver sampling distribution. Thus, it ignores any jitter tracking between data and clock signals. In this paper, a general formulation is presented to model the common jitter source between data and clock signals in order to capture any jitter tracking between them. To demonstrate the usage of the proposed formulation, we have derived various models for commonly used clocking architectures, such as the forwarded clocking scheme in XDR™, DDR, and GDDR systems and the common source RefClk architecture used in PCIe channels. The formulation is verified numerically by using an internally developed CAD tool.

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Modeling and Analysis of High-Speed I/O Links

Cited by 69 publications

References 14 publications

Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter

Clock jitter modeling in statistical link simulation

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