Clock jitter modeling in statistical link simulation

Abstract

Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling of data channels and the impact of a clock channel is often ignored or primitively approximated using a simple receiver sampling distribution. Thus, it ignores any jitter tracking between data and clock signals. In this paper, a general formulation is presented to model the common jitter source between data and clock signals in order to capture any jitter tracking between them. To demonstrate the usage of the proposed formulation, we have derived various models for commonly used clocking architectures, such as the forwarded clocking scheme in XDR™, DDR, and GDDR systems and the common source RefClk architecture used in PCIe channels. The formulation is verified numerically by using an internally developed CAD tool.

High-speed I/O jitter modeling methodologies

“…Receiver jitter can be modeled similarly except that for receiver jitter, the two impulses on the two bit edges have the same magnitude. Equivalent voltage noise at transmitter and receiver can be modeled together to model jitter tracking [3,9].…”

“…For example, if the clock channel has insufficient bandwidth, it will amplify highfrequency jitter such as DCD and severely limit link performance [7,8]. Moreover, if the same jitter is present on both clock and data path, its impact on link margin might be reduced (jitter tracking) or amplified (jitter anti-tracking), depending on the jitter frequency and the timing skew between the data and clock path [9]. For the rest of this section, we first discuss the characteristics of different link jitter sources such as reference clock random jitter and power supply induced jitter.…”

Plane bounce in high-speed single-ended signaling I/O interfaces

“…While this medium frequency noise has a significant effect on stable core power delivery, it is less critical for I/O signals. This is because most high-speed signaling technologies have a reference voltage and forwarded clock signal that can track low and medium frequency power noise, and its induced jitter [1] [2]. Furthermore, high-speed memory channels often use low-inductance BGA packages with power and ground planes, instead of inductive wire-bond or lead-frame packages.…”