Plane bounce in high-speed single-ended signaling I/O interfaces

Oh, Dan

doi:10.1109/epeps.2011.6100170

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…Various wireline transceivers with high pin/energy efficiency have been shown in previous studies 9–15 for high‐speed die‐to‐die links. However, their signaling could possess the downsides of traditional single‐ended signalings, including simultaneous switching noise, signal reference voltage offset, and frequency‐dependent signal return path, as described in Oh et al 16 …”

Section: Introductionmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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Section: Introductionmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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A general co-design approach to multi-level package modeling based on individual single-level package full-wave S-parameter modeling including signal and power/ground ports

Chen

2012

2012 IEEE 62nd Electronic Components and Technology Conference

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The power-aware SI (Signal Integrity) simulation takes into account the effect of the power supply noise. It is one of the key issues in the high-speed multi-level package system design. The multi-level package co-design requires a corresponding accurate modeling approach to include all signal, crosstalk and power noise effects to support the poweraware SI simulation.A general co-design approach to multi-level package modeling base on individual single-level package full-wave S-parameter modeling including signal and power/ground ports defined at chip-package and package-board vertical contact arrays is proposed in this paper with three features. Firstly, it includes not only the signal ports, but also the power and ground ports to support the power-aware SI simulations. Secondly, a port in the single-level model by this approach is seamlessly connectable to the corresponding port in another model by virtually connecting not only the port signal terminals, but also the port reference terminals. Thirdly, it combines package DC simulation and high-frequency fullwave simulation to guarantee wide band accuracy.A simple test case of a module-board-module with 20 ports on each module, and 20 ports on the board is used to verify the proposed method by both AC and nonlinear transient simulations.Another simple test case shows that the models by this approach can be used to fully model the transmission line structure in package even in the case of any transmission line referencing.

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Plane bounce in high-speed single-ended signaling I/O interfaces

Cited by 2 publications

References 4 publications

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A general co-design approach to multi-level package modeling based on individual single-level package full-wave S-parameter modeling including signal and power/ground ports

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