Model Reduction of Modules for State-Event Temporal Logics

Abstract

In many Discrete-Event Systems (DES) both state and event information are of importance to the systems designer. Logics such as Ostroff's RTTL allow for the specification and verification of a system's state-event behavior. To make realistic problems amenable to analysis, a designer must typically decompose the system into subsystems (modules) and use algebraic abstraction (quotient systems) to obtain hierarchical system models that preserve the properties to be verified. In this paper we use state-event observational equivalence to perform model reduction for a subclass of formulas of state-event linear temporal logics, with particular attention being paid to a discrete time temporal logic that is a simplification of RTTL. The reduction technique allows limited use of immediate operators.

A logical verification methodology for service-oriented computing

“…Usefulness of such a kind of models has been by now recognized in many contexts. For example, P/T systems [Kindler and Vesper 1998] have been introduced for Petri Nets modelling, State-Event LTSs [Lawford et al 1996] for real time modeling, Action-and-State Labelled Markov Chains [Baier et al 2004] [Müller-Olm et al 1999;Chaki et al 2004;Chaki et al 2005] for software verification. However, almost all the efforts towards the formal verification of SOC designs through model checking (a wide survey of the approaches based on WS-BPEL is presented in [van Breugel and Koshkina 2006]), rely on either LTSs or Kripke structures.…”

Composition and refinement of discrete real-time systems

“…It also describes how conditional specifications can be used to constrain module environments. Section 4 presents the refinement rule for modules based on the notion of observational equivalence of TTMs developed in Lawford et al [1996]. Observational equivalence of TTMs will be defined precisely in the sequel, but the reader is referred to Lawford and Wonham [1995] for a set of TTM equivalence-preserving transformations and to Lawford et al [1994] for an efficient polynomial-time algorithm to check TTM observational equivalence.…”

Formal verification of timed systems: a survey and perspective

“…Wang and Hsiung extended the technique to timed systems with concurrent read/write operations [223]. In [148] and [149], related work by Lawford et al on discrete-time systems can be found.…”