MOCVD Growth of InP on 4-inch Si Substrate with GaAs Intermediate Layer

Seki, Akinori; Konushi, F.; Kudo, J.; Kakimoto, Seizo; Fukushima, Takashi; Koba, Masayoshi

doi:10.1143/jjap.26.l1587

Cited by 31 publications

(7 citation statements)

References 7 publications

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“…MOVPE techiques, utilizing TMG(trimethylgallium), TMI (trimethylindium) for group ifi scoures and AsH3 or PH3 for group V sources, has been used for GaAs growth and InP growth, respectively. Seki et al reported residual stress in InP films of 5.7x10 dynlcm2 as compared to the value for InP grown directly on Si, 8.3 x 108 dyn/cm2 [52]. Some scattered results have been reported, however.…”

Section: Inp On Siliconmentioning

confidence: 98%

Lattice-mismatched elemental and compound semiconductor heterostructures for 2-D and 3-D applications

Lee

1991

SPIE Proceedings

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Research efforts to bring forth epitaxial integration of elemental semiconductors (Si,Ge) and compound semiconductors (GaAs, InP, ZnSe, CdTe) in various combination thereof, are reviewed. Also reviewed are the issues relating to the growth of insulating layers on semiconductor layers for the purpose of forming SOI (semiconductor-on-insulator) for potential applications in 2-D (two-dimensional) structures of 3-D (3-dimensional) superstructures. First, the physics and chemistry of heteroepitaxial processes are examined along with the issues stemming from the mismatches of lattice, thermal and chemical origin. Ways to ease mismatches, using epitaxial control or intermediate layers like strained-layer-superlattice, are examined including recent progresses. Prospects for future directions along with technological implications of the semiconductor heterostructures are discussed, including a brief account of the history related to this technology.

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Section: Inp On Siliconmentioning

confidence: 98%

Lattice-mismatched elemental and compound semiconductor heterostructures for 2-D and 3-D applications

Lee

1991

SPIE Proceedings

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“…Unlike the GaAs/Si, the InP/Si heteroepitaxy normally adopts the intermediate (graded) buffer layers because of the large lattice mismatch between InP and Si (~8%). The prevailing material commonly used for the intermediate buffer is GaAs [166][167][168][169]. The most typical approach for growing InP on Si is employing the mature multi-step growth of GaAs on Si with strained-layer superlattices filtering the TDs [149,170,171].…”

Section: Intermediate Buffer Layermentioning

confidence: 99%

“…Crystals 2020, 10, x FOR PEER REVIEW 16 of 40 commonly used for the intermediate buffer is GaAs [166][167][168][169]. The most typical approach for growing InP on Si is employing the mature multi-step growth of GaAs on Si with strained-layer superlattices filtering the TDs [149,170,171].…”

Section: Epitaxial Lateral Overgrowthmentioning

confidence: 99%

Heteroepitaxial Growth of III-V Semiconductors on Silicon

et al. 2020

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Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.

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“…The direct growth of InP on Si (001) substrates proved to be challenging due to the difficulty of InP nucleation on a Si surface and a common practice is to use a GaAs intermediate layer. 3,17 To solve the APB issue, atomic steps have been engineered on Si (001) substrates in the case of GaP growth. 12 In contrast to a Si surface, the double steps on a Ge surface can be formed at a lower temperature.…”

mentioning

confidence: 99%

Selective Area Growth of InP and Defect Elimination on Si (001) Substrates

Wang

Leys

Loo

et al. 2011

J. Electrochem. Soc.

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We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by using a thin Ge buffer layer. The antiphase domain boundaries in InP layers are suppressed by engineering the local Ge surface profile. The mechanism of atomic step formation and the corresponding method for step density control are presented. We discuss the impact of the surface profile of the Ge buffer layer on the formation of antiphase domain boundaries as well as on InP nucleation. A minimum step density of 0.25 nm1 is required to avoid antiphase domain boundaries while a higher step density substantially reduces the stacking faults and twins in the InP nucleation layer. By employing the threading dislocation necking effect and the properly controlled Ge surface profile, high-quality InP layers have been obtained in submicron trenches. VC 2011 The Electrochemical Society. [DOI: 10.1149/1.3571248] All rights reserved. Manuscript submitted January 31, 2011; revised manuscript received March 1, 2011. Published April 7, 2011. InP has been extensively used in high electron mobility transis-tors and heterojunction bipolar transistors.1,2 Recently, there has been arising interest in integrating InP and other high electron-mo-bility materials such as InGaAs on Si substrates to make high per-formance complementary metal oxide semiconductor (CMOS) devi-ces,3,4 One approach to integrate these materials on Si substrates i

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MOCVD Growth of InP on 4-inch Si Substrate with GaAs Intermediate Layer

Cited by 31 publications

References 7 publications

Lattice-mismatched elemental and compound semiconductor heterostructures for 2-D and 3-D applications

Lattice-mismatched elemental and compound semiconductor heterostructures for 2-D and 3-D applications

Heteroepitaxial Growth of III-V Semiconductors on Silicon

Selective Area Growth of InP and Defect Elimination on Si (001) Substrates

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