Mobility degradation due to the gate field in the inversion layer of MOSFET's

Fu, Kuan–Yu

doi:10.1109/edl.1982.25573

Cited by 41 publications

(13 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…We also determine E eff (V G ) in this section, which allows characterization of mobility using appropriate physical models (see section 5). Finally, we conclude this section by investigating the variation of Δμ eff (N IT ) using a well-known empirical mobility model [11,12,32,33].…”

Section: Device Details and Experimentsmentioning

confidence: 99%

“…To investigate the effect of interface traps on μ eff , we interpret the measured μ eff (section 3.2) through a well-known empirical mobility model for |V G |>>|V T | that has been widely used in circuit simulations [11,32,33,36], i.e.,…”

Section: Empirical Modeling Of μ Effmentioning

confidence: 99%

“…3 Table-I) under consideration. Comparison of these quantities (P 1 and P 2 ) for different type-I devices eliminates any EOT and substrate doping dependency of μ 0 and θ [32,33] -hence P 1 and P 2 only contain information related to nitrogen dependency for these devices. Fig.…”

Section: Compact δV T Estimation Algorithm For Type-i Devicesmentioning

confidence: 99%

See 2 more Smart Citations

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Islam

Maheta

Das

et al. 2008

2008 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

Mobility degradation due to generation of interface traps (Δμ eff (N IT )) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Δμ eff (N IT ) is relatively insignificant (compared to Δμ eff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis. Here, we investigate the importance of considering Δμ eff (N IT ) for reliability analysis by analyzing a wide variety of plasma oxynitride PMOS devices using both parametric and physical mobility models. We find that contrary to popular belief this correction is fundamentally important for robust and uncorrupted estimates of the key reliability parameters like threshold-voltage shift, lifetime projection, voltage acceleration factor, etc. Therefore, in this paper, we develop a generalized algorithm for estimating Δμ eff (N IT ) for plasma oxynitride PMOS devices and systematically explore its implications for NBTI-specific reliability analysis.

show abstract

Section: Device Details and Experimentsmentioning

confidence: 99%

Section: Empirical Modeling Of μ Effmentioning

confidence: 99%

See 1 more Smart Citation

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Islam

Maheta

Das

et al. 2008

2008 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

show abstract

“…According to Ref [30,31], the voltage-dependent effective mobility (µeff) of SiO2/etched GaN channel is only about 16 cm 2 /V·s. This value is much lower than the low-field electron mobility (µ0) and µeff of the planar HEMT equal to 1560 and 700 cm 2 /V·s at VG = 2 V, respectively, extracted using a mobility-degradation model [32,33]. The µ0 was close to the Hall mobility, which was about 1660 cm 2 /V·s.…”

Section: Resultsmentioning

confidence: 85%

Enhanced Electrical Performance and Heat Dissipation in AlGaN/GaN Schottky Barrier Diodes Using Hybrid Tri-anode Structure

Santoruvo

Tandon

et al. 2016

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-Enhanced performance in AlGaN/GaN Schottky barrier diodes (SBDs) is investigated using a nanowire hybrid tri-anode structure that integrates three-dimensional Schottky junctions with tri-gate transistors. The fabricated SBDs presented an increased output current density with improved linearity, above 1 A/mm at 5 V when normalized by effective anode width, over 3 orders of magnitude lower reverse leakage current and superior heat dissipation. The sidewall Schottky contacts reduced the turn-on voltage and eliminated the non-ideality caused by the AlGaN barrier. The large surface area of tri-gate architecture greatly enhanced heat dissipation and largely reduced the average temperature as well as thermal resistance of the integrated tri-gate transistors. The trench conduction near SiO2/GaN interface, formed under forward bias at both sidewalls and bottom of nanowire trenches, compensated part of the self-heating degradation and improved the output linearity of the device. Optimal design for the tri-anode structure, based on a model of critical filling factor, was proposed to surmount the issue of partial removal of two-dimensional electron gas (2DEG), unveiling the potential of nanostructured GaN devices to achieve comparable or even larger output current than counterpart planar devices.

show abstract

“…However, the argument above is not quite the same as for FinFET. In FinFET, can be expressed as [17] where C ox is the gate oxide capacitance and B is a constant. Eqn (2) means mobility degradation factor is a function of charge density in depletion layer, which is presumably diminished by the fully-depleted bulk in FinFET architecture.…”

Section: Nbti Stressmentioning

confidence: 99%

Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors

Lee

Chen

Lee

et al. 2015

2015 IEEE International Integrated Reliability Workshop (IIRW)

View full text Add to dashboard Cite

Despite chip-package interaction (CPI) has been extensively used in nano-electronics industry, impact of CPI stress on transistor performance and reliability remains unclear. In this work, performance change of transistor featuring HK/MG planar and FinFET by 4-point bending experiments were conducted to study stress evolution. Finite-element modeling (FEM) simulation revealed that P-FinFET mobility change is less sensitive to applied stress than planar. Device reliability as BTI/HCI and ring oscillator frequency drift of both planar and FinFET are all immune to strain. Moreover, FinFET mobility degradation caused by NBTI is independent of strain type, due to its fully-depleted regime. Management of carrier mobility shifts and transistor aging by optimized chip package technology are also presented in this study.

show abstract

Mobility degradation due to the gate field in the inversion layer of MOSFET's

Cited by 41 publications

References 2 publications

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Enhanced Electrical Performance and Heat Dissipation in AlGaN/GaN Schottky Barrier Diodes Using Hybrid Tri-anode Structure

Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors

Contact Info

Product

Resources

About