Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors

Lee, Jen-Hao; Chen, Eliot S.H.; Lee, Yung-Huei; Lin, Cheng-Piao; Wu, C. M.; Hsieh, Meng-Kuei; Huang, Kevin; Wang, Jhong-Sheng; Tsai, Y. S.; Lu, Ryan; Shih, J.R.

doi:10.1109/iirw.2015.7437068

Cited by 2 publications

(1 citation statement)

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“…For CMOS devices, the results of stress variations across the die leads to timing variability that must be accounted for with design margins. Prior studies by Intel [8] and TSMC [9] observed qualitatively similar results in ROs fabricated in test chips that were used to investigate the effects of package overmolding on induced stress and resulting circuit timing variation.…”

Section: E Ring Oscillator Behavior After Thinning and Temperature Cyclingmentioning

confidence: 64%

Impacts of Substrate Thinning on FPGA Performance and Reliability

Leonhardt

Beechem

Cannon

et al. 2021

International Symposium for Testing and Failure Analysis

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Global thinning of integrated circuits is a technique that enables backside failure analysis and radiation testing. Prior work also shows increased thresholds for single-event latchup and upset in thinned devices. We present impacts of global thinning on device performance and reliability of 28 nm node field programmable gate arrays (FPGA). Devices are thinned to values of 50, 10, and 3 microns using a micromachining and polishing method. Lattice damage, in the form of dislocations, extend about 1 micron below the machined surface. The damage layer is removed after polishing with colloidal SiO2 slurry. We create a 2D finite-element model with liner elasticity equations and flip-chip packaged device geometry to show that thinning increases compressive global stress in the Si, while C4 bumps increase stress locally. Measurements of stress using Raman spectroscopy qualitatively agree with our stress model but also reveal the need for more complex structural models to account for nonlinear effects occurring in devices thinned to 3 microns and after temperature cycling to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning but the maximum temperature difference across the 3-micron die is less than 2°C. Ring oscillators (ROs) programmed throughout the FPGA fabric slow about 0.5% after thinning compared to full thickness values. Temperature cycling the devices to 125°C further decreases RO frequency about 0.5%, which we attribute to stress changes in the Si.

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Section: E Ring Oscillator Behavior After Thinning and Temperature Cyclingmentioning

confidence: 64%