MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

Abstract

With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading the development of lightweight embedded systems. However, as the IoT era gets more sophisticated, existing ULP processors are expected to reach a critical limit in the absence of a memory management unit (MMU) in that multiple programs cannot be run in the MMU-less embedded systems. To tackle this issue, we propose an architecture in which the MMU is embedded in a network-on-chip (NoC). Through the proposed approach, NoC offers MMU functionality without modifying the processor design, allowing developers to easily leverage the existing ULP lightweight processors and build embedded systems that support multiprocessing. In this paper, along with the details of the proposed MMU-embedded NoC (MMNoC) design, a prototype platform including the MMNoC and dual RISC-V processors is provided. The prototype platform is synthesized with FPGA and Samsung 28 nm FD-SOI technology to verify the functional accuracy and small performance, area, and power overhead of the MMNoC. INDEX TERMS Network-on-chip, NoC, memory management unit, MMU, embedded system.

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

“…For supporting only the essential communication features, the NIs perform protocol conversion between various IPs with different interfaces in an SoC. They support conversions among AXI, AHB, and advanced peripheral bus (APB) protocols that are the most representative advanced microcontroller bus architecture (AMBA) specifications [35]- [39], and for 32, 64, and 128 b. For the router design, we focus on the routing functionality and thus do not optimize other features to enhance performance, such as an adaptive routing considering network traffic or speculative execution in router pipelining.…”

Developing a Multicore Platform Utilizing Open RISC-V Cores

“…The TCU is written in Verilog hardware description language at register-transfer level, and is verified on a Xilinx FPGA. We first paid attention to the bus interface for communication between the core and the memory, and designed the TCU targeting the most commonly used AXI protocol [28], [29].…”

“…Owing to the ability of NoC to overcome the limitations of the conventional busbased system interconnects (e.g., unbearable increasing density and complexity induced by the system interconnect) [27], [30], [31], NoC is commonly used in the state-of-the-art multicore platforms. FIGURE 12 (a) shows the conventional NoC architecture, and the processor core in the platform communicates with other IPs only through the dedicated network interface (NI) of NoC [28], [32]. Therefore, since the developed TCU operates independently between the core and the network, if it is embedded in NI, TC can be realized on the platform no matter what cores are used.…”