A technology for low-power high data-rate digital capsule endoscopy with human body communication (CEHBC) is presented in this paper. To transfer the image data stably with low power consumption, the proposed system uses three major schemes: Frequency selective digital transmission (FSDT) modulation with HBC, the use of an algorithm to select electrode pairs, and the LineSync algorithm. The FSDT modulation supports high-data rate transmission and prevents the signal attenuation effect. The selection algorithm of the electrode pair finds the best receiving channel. The LineSync algorithm synchronizes the data and compensates for data polarity during the long data transmission section between the capsule endoscope and the receiver. Because all the major functional blocks of the CEHBC transmitter can be implemented as digital logics, they can be easily fabricated using the field programmable gate array (FPGA). Moreover, this CEHBC transmitter can achieve low power-consumption and can support a relatively high data rate in spite of using its clock a few tens of MHz slower. The proposed CEHBC-TXD is the digital portion of the CEHBC transmitter that provides low-power (3.7 mW) and high data-rate (6 Mbps) performance while it supports a high-resolution image (480 × 480 byte) at 3.13 fps.
A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage.
In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 μA to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm2. We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things.
This paper presents a transmission method for improving human body communications in terms of spectral efficiency, and the performances of bit‐error‐rate (BER) and frame synchronization, with a highly simplified structure. Compared to the conventional frequency selective digital transmission supporting IEEE standard 802.15.6 for wireless body area networks, the proposed scheme improves the spectral efficiency from 0.25 bps/Hz to 1 bps/Hz based on the 3‐dB bandwidth of the transmit spectral mask, and the signal‐to‐noise‐ratio (SNR) by 0.51 dB at a BER of 10−6 with an 87.5% reduction in the detection complexity of the length of the Hamming distance computation. The proposed preamble structure using its customized detection algorithm achieves perfect frame synchronization at the SNR of a BER of 10−6 by applying the proposed pre‐processing to compensate for the distortions on the preamble signals due to the band‐limit effects by transmit and receive filters.
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