Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Abstract

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 • C and 0.44 V at 80 • C while continuing to operate at a target 50-MHz clock frequency.

A Study of Advancing Ultralow-Power 3D Integrated Circuits with TEI-LP Technology and AI-Enhanced PID Autotuning

“…We have confirmed through previous studies that this TEI benefit is evident across the entire operating temperature range of the chip (typically from −25 °C to 125 °C) in various semiconductor technology processes [19,27]. TEI-LP techniques exploit the TEI benefit through various approaches, such as TEIaware voltage scaling (VS) [22,24,27,30], frequency scaling (FS [21], body biasing (BB) [26], or dynamic power management (DPM) [25]. Among these, the best-known technique is TEI-aware VS (TEI-VS), which converts the TEI benefit into power savings through voltage downscaling.…”

“…As T increases, the difference in delay, resulting from τ target , becomes more significant, and this delay margin, as shown in Figure 1, is defined as the TEI benefit. We have confirmed through previous studies that this TEI benefit is evident across the entire operating temperature range of the chip (typically from −25 °C to 125 °C) in various semiconductor technology processes [19,27]. TEI-LP techniques exploit the TEI benefit through various approaches, such as TEIaware voltage scaling (VS) [22,24,27,30], frequency scaling (FS [21], body biasing (BB) [26], or dynamic power management (DPM) [25].…”

“…In our recent research, we designed an ultralow-power (ULP) system-on-chip (SoC) based on ULV circuitry and fabricated it using a 28 nm FDSOI process [27]. We demonstrated the significant effectiveness of TEI-VS with this chip, and Figure 2 reports the results of applying TEI-VS at 10 • C intervals.…”

“…Over the past decade, we have conducted in-depth research on ULV circuits, focusing on the unique phenomenon where circuit speed increases with rising temperature [18], termed the temperature effect inversion (TEI) phenomenon [19]. We have dedicated our efforts to developing TEI-aware low-power (TEI-LP) techniques, which are now in a mature state [20][21][22][23][24][25][26][27]. Furthermore, we have recently developed a processor chip using the 28nm FDSOI process, incorporating the TEI-LP technology.…”

Developing a Multicore Platform Utilizing Open RISC-V Cores

“…In a previously published paper [33], we introduced a new electronic design automation (EDA) tool, RISC-V eXpress (RVX), that allows the SoC developers to quickly and easily create SoC platforms using a variety of RISC-V cores. Indeed, there are many open source RISC-V cores and it is not difficult to acquire them, but the process of developing SoCs using such open source cores is very complex, which requires a lot of time and effort with high design skills and experience.…”