MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows

Goswami, Pingakshya; Shahshahani, Masoud; Bhatia, Dinesh

doi:10.1109/lascas53948.2022.9789084

Cited by 4 publications

(1 citation statement)

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“…In addition, Makrani [7] has modeled time optimization as a regression problem and used DL to evaluate the clock frequency of the HLS tool's output code. In [8], the authors proposed a methodology to address the challenge of the availability of open-source HLS designs for training and prediction of DL models. They present a methodology for generating diverse designs with various variations from a single design, resulting in a dataset of synthesizable FPGA HLS designs.…”

Section: B Synthesismentioning

confidence: 99%

Unraveling the Integration of Deep Machine Learning in FPGA CAD Flow: A Concise Survey and Future Insights

Ghavami¹,

Shannon²

2023

Preprint

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This paper presents an overview of the integration of deep machine learning (DL) in FPGA CAD design flow, focusing on high-level and logic synthesis, placement, and routing. Our analysis identifies key research areas that require more attention in FPGA CAD design, including the development of open-source benchmarks optimized for end-to-end machine learning experiences and the potential of knowledge-sharing among researchers and industry practitioners to incorporate more intelligence in FPGA CAD decision-making steps. By providing insights into the integration of deep machine learning in FPGA CAD flow, this paper aims to inform future research directions in this exciting and rapidly evolving field.

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Section: B Synthesismentioning

confidence: 99%