Mixed-Mode Simulation and Analysis of Digital Single Event Transients in Fast CMOSICs

Turowski, Marek; Raman, Ashok; Jablonski, Grzegorz

doi:10.1109/mixdes.2007.4286199

Cited by 26 publications

(16 citation statements)

References 11 publications

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“…Device model parameters are consistent with other transistor model in which the same technology is used. The doping profiles are calibrated within the 3-D model by process simulation and an inverse modeling approach [14] and are consistent with the I-V characteristics between TCAD and SPICE simulations. The PMOS struck by particles and the adjacent PMOS use 3-D model whereas other NMOS and PMOS transistors use SPICE model.…”

Section: Simulation Setupmentioning

confidence: 73%

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Qin

Chen

Liu

et al. 2011

Sci. China Technol. Sci.

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Since single event transient pulse quenching can reduce the SET (single event transient) pulsewidths effectively, the charge collected by passive device should be maximized in order to minimize the propagated SET. From the perspective of the layout and circuit design, the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay, which sheds new light on the radiation-hardened ICs (integrated circuits) design. Studies show that the SET pulsewidths of propagation are not in direct proportion to the LET (linear energy transfer) of incident particles, thus the defining of the LET threshold should be noted when SET/SEU (single event upset) occurs for the radiation-hardened design. The capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is low. Therefore, radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit. SET propagation, radiation hardening by design, charge collection, charge share, quenching Citation: Qin J R, Chen S M, Liu B W, et al. Research on single event transient pulse quenching effect in 90 nm CMOS technology.

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Section: Simulation Setupmentioning

confidence: 73%

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Qin

Chen

Liu

et al. 2011

Sci. China Technol. Sci.

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“…Simulation may support this and help to reduce the costs in terms of stress tests. Three dimensional physical simulations of ionizing radiation effects in the semiconductor structure, which are coupled to an external circuit simulator are one way to do so [11].…”

Section: Simulation Of Iterationmentioning

confidence: 99%

“…The reaction on a radiation event is in technology nodes beyond 100nm closely related to the structure of the device caused by the presence of interconnects, bias, and different metallization layers affecting the performance [11][12][13].…”

Section: Simulation Of Iterationmentioning

confidence: 99%

COTS – Harsh Condition Effects Considerations from Technology to User Level

Weide‐Zaage¹,

Payá-Vayá²

2017

Adv. sci. technol. eng. syst. j.

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“…And in another domain, Technology CAD (TCAD) and two-dimensional (2-D) or three-dimensional (3-D) devicelevel simulation are typically used to provide excellent insight into detailed device operation. Combination of these two, so called mixed-mode or mixed-level simulators, replaces certain compact devices in a circuit description with TCAD-modeled devices, and obtains results consistent with experiments [7] while speed up the simulation greatly compared to full TCAD simulation. However, mixed-mode simulation is still time costly and thus hard to apply in large scale circuits.…”

Section: Introductionmentioning

confidence: 99%

“…However, when the response time of the circuit is below 200ps, it can not be neglected in influencing the charge collection process. Turowski [7] analyzed this limitation of PWL method in detail. And moreover, this point is especially notable in analog circuit, e.g., VCO.…”

Section: A Introduction Ofsingle Event Transientsmentioning

confidence: 99%

Verilog-A based implementation for coupled model of single event transients in look-up table technique

Zhao

Zhang

2009

2009 IEEE 8th International Conference on ASIC

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A Verilog-A based implementation of voltage coupled model is developedfor Single-Event Transients (SETs) in microelectronic circuits. By implementing a look-up table in Verilog-A, the SET current source performs well and consents with the results from Technology CAD (TCAD) based mix-mode simulation. Simulation results from Synopsys Hspice 2008 indicates that the method proposed in this paper correctly reveals the current "tail" which reflects the equilibrium course of charge collection. Moreover, the Verilog-A based method speeds up the simulation by over 18,000 times than the mix-mode simulation and is also faster than the piecewise linear source (PWL).Furthermore, this Verilog-A based LUT method cooperates with the design flow well and can be easily applied to various applications with wide supports ofindustrial EDA tools}.

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Mixed-Mode Simulation and Analysis of Digital Single Event Transients in Fast CMOSICs

Cited by 26 publications

References 11 publications

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Research on single event transient pulse quenching effect in 90 nm CMOS technology

COTS – Harsh Condition Effects Considerations from Technology to User Level

Verilog-A based implementation for coupled model of single event transients in look-up table technique

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