Mixed-dimensional van der Waals heterostructures

Jariwala, Deep; Marks, Tobin J.; Hersam, Mark C.

doi:10.1038/nmat4703

Cited by 1,321 publications

(1,118 citation statements)

References 144 publications

Supporting

Mentioning

1,092

Contrasting

Unclassified

Order By: Relevance

“…With previously reported fabrication methods, p-n vdWHs, whether lateral or vertical, consisted of a p-n heterojunction connected by two lateral p-type and n-type extensions (acting as FETs in series) or Schottky diodes with graphene, with the overall stack being coupled to one or two gates with alignment errors increasing with each component. [7][8][9][26][27][28][29][30][31] In the lateral geometry, p-n vdWHs offer electrostatically controlled doping in the constituent semiconductors but suffer from large parasitic resistance from the lateral extensions beyond the junction region. [7][8][9][28][29][30] On the other hand, vertical p-n vdWHs that employ a graphene electrode can achieve larger current density at the cost of defect-induced leakage currents, extraneous Schottky barriers, and electrode screening issues.…”

Section: Toc Imagementioning

confidence: 99%

See 1 more Smart Citation

Self-Aligned van der Waals Heterojunction Diodes and Transistors

et al. 2018

Self Cite

View full text Add to dashboard Cite

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of anti-ambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated anti-ambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. 2For example, the versatility of this scheme is demonstrated via contact-doped MoS2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150 nm to 800 nm using photolithography on large-area MoS2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step towards the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems. TOC IMAGE 3Parallel self-aligned fabrication methods in modern silicon-based microelectronics have enabled sub-lithographic registration between processing steps, ultimately facilitating substantial advances in circuit complexity over the past few decades. 1 In contrast, while two-dimensional (2D) materials have shown significant potential for digital and analog electronics due to their high mobilities, ultrathin geometry, and broad range of permutations in van der Waals heterojunctions (vdWHs), 2-9 2D material devices have not yet exploited parallel self-aligned fabrication to achieve both short channels and large area fabrication. Thus far, short-channel 2D material transistors and vdWHs have been achieved using serial processing methods such as electron-beam lithography or mechanical placement on nanotube or nanowire gates. 5,10,11 Similarly, the relative alignment of different layers in vdWHs has been inhibited by the diffraction-limited resolution of transfer and alignment methods. Here, we overcome these limitations by introducing a self-aligned processing methodology that enables the fabrication of 2D material transistors with channel lengths below 150 nm with minimal short-channel effects and improved current saturation, as demonstrated with monolayer MoS2. These self-aligned transistors show the highest output resistance at the lowest channel length reported for a 2D material, which is of interest for high-frequency current amplifiers and mixers. In vdWHs based on black phosphorus (BP) and MoS2, this self-aligned approach allows dual-gate ...

show abstract

Section: Toc Imagementioning

confidence: 99%

“…S2.15). 26 Furthermore, this selfaligned method is straightforwardly extended to large areas without compromising lateral spatial resolution as demonstrated by photolithographically defined SASC transistors on continuous MoS2 films with sub-wavelength channel lengths (~150 nm) (Supporting Fig. S2.16).…”

Section: Toc Imagementioning

confidence: 99%

Self-Aligned van der Waals Heterojunction Diodes and Transistors

et al. 2018

Self Cite

View full text Add to dashboard Cite

show abstract

“…The contact between silver paste and graphene is physically formed by van der Waals interaction as was reported previously. [5] The Ag-G contact can be considered as metal-vacuum-graphene junction with relatively rough porous paste. As a result, the contact resistance is high and the capacitance is relatively low.…”

Section: Impedance Spectroscopy Analysismentioning

confidence: 99%

“…[1][2][3] In particular, the graphene-semiconductor or graphene-silicon (GS) Schottky diodes are one of the simplest possible heterostructure devices consisting of a conventional 2D semiconducting material and a 2D metallic material. [4,5] These heterostructures can act as rectifiers, potential barrier modulators, photodetectors, photovoltaic devices, chemical sensors, etc. [6][7][8][9][10][11][12] Even though GS Schottky diodes are relatively simple to fabricate, their performance is limited by the various factors which can be measured by the ideality factor (η).…”

Section: Introductionmentioning

confidence: 99%

Origin of Voltage‐Dependent High Ideality Factors in Graphene–Silicon Diodes

Park

Choi

2017

Adv Elect Materials

View full text Add to dashboard Cite

devices, the hurdle should be overcome by identifying the origin. However, the origin of the wide-range ideality factor was not yet been fully elucidated.The ideality factor is a measure of how efficiently an applied bias is delivered to the junction of the device. The ideality factor of GS devices can be influenced by both voltage-independent serial resistance and voltage-dependent attributes such as interface state and quantum capacitance. Thus, one can expect that the ideality factor changes with applied bias voltage.First of all, when a bias voltage is applied to a GS junction, the Fermi level of 2D graphene changes significantly in contrast to typical metal-oxide-semiconductor (MOS) devices due to the far less density of states of graphene compared to that of 3D metal. As a result, the effective Schottky barrier height and the resistance of graphene change with bias voltage. This directly influences the GS device performance and the ideality factor.Second, a peculiar issue related to the GS devices is the un avoidable wet graphene transfer process on a cleaned silicon wafer. During this process, oxidation of silicon occurs naturally. As a result, the GS devices inevitably have a native interfacial oxide layer between graphene and silicon although it may be very thin. This interfacial oxide layer directly influences the performance of GS devices. Although the layer can act as a tunneling barrier, which may enhance the effective potential barrier height, this effect has often been ignored because the layer is thin enough to assume that the transport property is largely governed by the semiconductor rather than limited by the tunneling.Third, the truncated silicon surface has high density of surface states. The surface states can exist as interface states of GS devices. The interface states can be equilibrated with silicon itself or with the graphene and this depends on the thickness of the interfacial oxide layer. Due to the very thin native oxide layer, one can expect that the silicon interface state can be mostly equilibrated with graphene rather than silicon itself. But this has not been confirmed yet.In this study, first we extract the voltage-dependent ideality factors of graphene-silicon Schottky diodes from their I-V characteristics based on Schottky emission theory. [13][14][15] We then compare the ideality factors with those obtained from the impedance spectra. [16,17] We designed an equivalent circuit model for analysis of impedance spectra accounting for Undoubtedly graphene-silicon (GS) heterostructure devices will play significant roles as future rectifiers, potential barrier modulators, photodetectors, photovoltaic devices, biochemical sensors, and so on. However, typical GS devices suffer from unusually wide-range voltage-dependent high ideality factors (η = 1.1-33.5). To overcome this hurdle, the origin of this wide-range voltage-dependent ideality factor should first be identified but this has not yet been fully studied. This study focuses on identifying the origin using impedance spectroscop...

show abstract

“…In addition to the 2D material-based optoelectronics in the above discussions, 2D material-based heterostructures have been reported to show excellent performance for optoelectronic applications in the previous literatures [84][85][86][87][88][89]. By stacking different 2D semiconducting crystals on top of each other with van der Waals-like forces, those heterostructures are expected to show combined functionality of the individual layers and new phenomena at the interface.…”

Section: Hot Electron Injectionmentioning

confidence: 96%

Photonic Structure-Integrated Two-Dimensional Material Optoelectronics

Wang

2016

Electronics

View full text Add to dashboard Cite

Abstract:The rapid development and unique properties of two-dimensional (2D) materials, such as graphene, phosphorene and transition metal dichalcogenides enable them to become intriguing candidates for future optoelectronic applications. To maximize the potential of 2D material-based optoelectronics, various photonic structures are integrated to form photonic structure/2D material hybrid systems so that the device performance can be manipulated in controllable ways. Here, we first introduce the photocurrent-generation mechanisms of 2D material-based optoelectronics and their performance. We then offer an overview and evaluation of the state-of-the-art of hybrid systems, where 2D material optoelectronics are integrated with photonic structures, especially plasmonic nanostructures, photonic waveguides and crystals. By combining with those photonic structures, the performance of 2D material optoelectronics can be further enhanced, and on the other side, a high-performance modulator can be achieved by electrostatically tuning 2D materials. Finally, 2D material-based photodetector can also become an efficient probe to learn the light-matter interactions of photonic structures. Those hybrid systems combine the advantages of 2D materials and photonic structures, providing further capacity for high-performance optoelectronics.

show abstract

Mixed-dimensional van der Waals heterostructures

Cited by 1,321 publications

References 144 publications

Self-Aligned van der Waals Heterojunction Diodes and Transistors

Self-Aligned van der Waals Heterojunction Diodes and Transistors

Origin of Voltage‐Dependent High Ideality Factors in Graphene–Silicon Diodes

Photonic Structure-Integrated Two-Dimensional Material Optoelectronics

Contact Info

Product

Resources

About