Origin of Voltage‐Dependent High Ideality Factors in Graphene–Silicon Diodes

Abstract

devices, the hurdle should be overcome by identifying the origin. However, the origin of the wide-range ideality factor was not yet been fully elucidated.The ideality factor is a measure of how efficiently an applied bias is delivered to the junction of the device. The ideality factor of GS devices can be influenced by both voltage-independent serial resistance and voltage-dependent attributes such as interface state and quantum capacitance. Thus, one can expect that the ideality factor changes with applied bias voltage.First of all, when a bias voltage is applied to a GS junction, the Fermi level of 2D graphene changes significantly in contrast to typical metal-oxide-semiconductor (MOS) devices due to the far less density of states of graphene compared to that of 3D metal. As a result, the effective Schottky barrier height and the resistance of graphene change with bias voltage. This directly influences the GS device performance and the ideality factor.Second, a peculiar issue related to the GS devices is the un avoidable wet graphene transfer process on a cleaned silicon wafer. During this process, oxidation of silicon occurs naturally. As a result, the GS devices inevitably have a native interfacial oxide layer between graphene and silicon although it may be very thin. This interfacial oxide layer directly influences the performance of GS devices. Although the layer can act as a tunneling barrier, which may enhance the effective potential barrier height, this effect has often been ignored because the layer is thin enough to assume that the transport property is largely governed by the semiconductor rather than limited by the tunneling.Third, the truncated silicon surface has high density of surface states. The surface states can exist as interface states of GS devices. The interface states can be equilibrated with silicon itself or with the graphene and this depends on the thickness of the interfacial oxide layer. Due to the very thin native oxide layer, one can expect that the silicon interface state can be mostly equilibrated with graphene rather than silicon itself. But this has not been confirmed yet.In this study, first we extract the voltage-dependent ideality factors of graphene-silicon Schottky diodes from their I-V characteristics based on Schottky emission theory. [13][14][15] We then compare the ideality factors with those obtained from the impedance spectra. [16,17] We designed an equivalent circuit model for analysis of impedance spectra accounting for Undoubtedly graphene-silicon (GS) heterostructure devices will play significant roles as future rectifiers, potential barrier modulators, photodetectors, photovoltaic devices, biochemical sensors, and so on. However, typical GS devices suffer from unusually wide-range voltage-dependent high ideality factors (η = 1.1-33.5). To overcome this hurdle, the origin of this wide-range voltage-dependent ideality factor should first be identified but this has not yet been fully studied. This study focuses on identifying the origin using impedance spectroscop...

High Responsivity and Detectivity Graphene-Silicon Majority Carrier Tunneling Photodiodes with a Thin Native Oxide Layer

“…In the forward bias region, the capacitance decreases slowly as the forward bias voltage decreases but does not depend on the optical light illumination as expected. The plateau shown between 0 and 1 V is related to the interface states as mentioned above, which are significantly large in the graphene–silicon interface as identified in the precious study …”

“…Additionally, the Cheung’s method is employed (inset of Figure b) when the bias voltage is limited in the forward bias voltage range (1.3 V ∼ 3 V). The extracted physical parameters show a difference in SBH, serial resistance, and ideality factor from those extracted by the direct fitting, as shown in Table . ,, This clearly indicates that the physical parameters depend on the applied bias voltage, while the native oxide thickness ( d ) is estimated as ∼0.42 nm in both cases.…”

“…A graphene layer was synthesized on a polished copper (Cu) foil (∼100 μm in thickness) using a conventional chemical vapor deposition (CVD) growth method. − The Cu foil (area of 7 mm × 7 mm) was etched by Fe 2 Cl 3 etchant solution after deposition a poly methyl methacrylate (PMMA) layer on the grown graphene/Cu layer. The residue of Fe 2 Cl 3 etchant was rinsed by deionized (DI) water in several times. , …”

“…This indicates that the effective SBH in the low bias region is higher than at the higher bias voltage. This can be attributed to the high density interface states …”

“…Based on the SBH and the work function difference between graphene and silicon, the silicon Fermi level may be at 4.69 eV, which is inconsistent with 4.86 eV estimated from the C – V study (see Figure S1, Supporting Information) and the extracted information on the silicon conductivity provided by the vendor. The inconsistency is attributed to Fermi level pinning caused by the high density interface states at the silicon surface . However, the SBH becomes lower due to the oxide voltage ( V OX ) and the voltage-dependent graphene Fermi level shift (Δ E F G ) with the reverse bias voltages.…”