Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

Sumita, M.; Sakiyama, Shiro; Kinoshita, Masayoshi; Araki, Y.; Ikeda, Y.; Fukuoka, Kazuki

doi:10.1109/jssc.2004.838013

Cited by 17 publications

(7 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The threshold voltage can be controlled in many ways [10][11][12]; one method is to control source-bulk voltage. The threshold voltage can be controlled in many ways [10][11][12]; one method is to control source-bulk voltage.…”

Section: Introductionmentioning

confidence: 99%

“…The threshold voltage is one of the effective parameters of power consumption and speed in very large scale integration circuits. The threshold voltage can be controlled in many ways [10][11][12]; one method is to control source-bulk voltage. This approach can be easily implemented with silicon on insulator (SOI) technology, but its high costs and difficulties in manufacturing transistors limit its usage [13].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

New SRAM design using body bias technique for low‐power and high‐speed applications

Faraji¹,

Naji²,

Rahimi-Nezhad³

et al. 2013

Circuit Theory & Apps

View full text Add to dashboard Cite

In this paper, a new SRAM cell with body-bias actively controlled by a control circuit and word line is introduced to realize low-power and high-speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade-off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

New SRAM design using body bias technique for low‐power and high‐speed applications

Faraji¹,

Naji²,

Rahimi-Nezhad³

et al. 2013

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Besides, the environmental temperature variation changes the mobility of the electrons and holes while modifying V TH of the devices, thus causing the circuit speed variation [1], [3], [4]. On top of that, the supply voltage V DD is another critical parameter that directly affects the transient current of the digital circuits, because the saturation current of the transistor is proportional to α/(V DD − V TH ), where α is the carrier mobility degradation factor [3], [5].…”

Section: Introductionmentioning

confidence: 99%

“…Through summing up these effects, the digital system will exhibit a wide deviation of performance, particularly significant in nanometer CMOS technologies. To tackle this issue, many techniques have been reported to compensate the process [2]- [4], [6]- [15] and temperature [4], [16] variations.…”

Section: Introductionmentioning

confidence: 99%

“…The compensation techniques on the basis of substrate bias control to change V TH of the transistor are extensively reported [2]- [4], [6]- [16]. It is common to observe that the effect of the substrate terminal on controlling V TH of the transistor is greatly reduced due to relatively lower body bias factor in advanced nanometer CMOS process technology.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation

Xiao

Chan

2016

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

This paper presents a fully integrated process, supply voltage, and temperature compensated supply (PVTCS) for a point-of-load digital system. Through adding the appropriate weighted threshold voltage variation from the pMOS ( V THP ) and the nMOS ( V THN ) diodes to the reference voltage of a high-speed low-dropout voltage regulator, the supply of the digital circuit becomes adaptive, and hence, it minimizes the speed deviation in the context of PVT variations. Validated in a UMC 65-nm CMOS process, the simulation and the measurement results of an inverter chain-based oscillator have validated the effectiveness of PVTCS. It can significantly reduce the delay variations with respect to the uncompensated supply counterpart. The same goes for a sample critical path-based oscillator with extensive simulation results. Therefore, the proposed circuit is useful for the digital point-of-load application, with the key technical merit of PVT compensation without encountering the potential latch-up problem from the reported methods.

show abstract