MIPA4k: A 64×64 cell mixed-mode image processor array

Abstract

This paper presents the MIPA4k, a 64x64 cell mixed-mode image processor array chip. The processor cell includes an image sensor, A/D/A conversion, embedded digital and analog memories and hardwareoptimized grayscale and binary processing cores. This paper presents the architecture of the processor cell and the different functional hardware. The processor has been manufactured in a 0.13 micron CMOS technology and the chip size is 5.1x4.5 mm 2 with a cell area of 72x61 µm 2 .978-1-4244-3828-0/09/$25.00 ©2009 IEEE

Visual Odometry for Pixel Processor Arrays

“…PPA sensors consist of a parallel array of neighborconnected processing elements, each of which features light capture, processing and storage capabilities allowing for various image processing tasks to be efficiently performed directly on the focal plane itself [4], [15], [9], [1], [2], [19]. This is in contrast to traditional camera sensors in which each pixel element is only capable of light capture, meaning that whole images must be transferred to a separate external device for processing.…”

Mixed signal SIMD processor array vision chip for real-time image processing

“…Recent vision chips, in common with the chip described here, operate as SIMD computational devices; such devices have been presented widely in both digital [8][9][10], analogue [11][12][13][14] and mixed signal form [15,16]. Designers of wholly digital vision chips have tended to adopt larger cell sizes (65 9 25 lm [8], 67 9 64 lm [9] and 51 9 54 lm [10]) than their analogue (49 9 49 lm [11], 35 9 35 lm [12], 34 9 29 lm [13], 26 9 26 lm [14]) counterparts.…”

“…However, while utilizing lower cost processes, specifically 0.18 lm, analogue processors can achieve bit-equivalent memories and ALUs similar to their digital counterparts in a more compact space. The relatively high pixel pitch of all recent vision chips [8][9][10][11][12][13][14][15][16] limits the pixel count to typically \20 kpixels, making them suitable for applications in which high speed or low power is required, but very high spatial resolution is not essential, for example, surveillance systems [7,17], performing on-line analysis in industrial production systems [4], or providing vision systems for robots [18]. The separation of processing and imaging areas (described in [8]) removes some of the constraints on occupied PE silicon space resulting in low fill factor; the design compromise made for this approach is that algorithms must start by reading out data from the array into the close-connected PEs; for fast image processing, frame rates might be slowed by this process.…”

Focal plane generation of multi-resolution and multi-scale image representation for low-power vision applications

“…[4][5][6] These chips implement a massively parallel focal-plane array where each pixel does not consist only of a simple photosensor but also includes analog processing circuitry. The resulting pixel-level processor is usually 4-or 8-connected to its neighbors rendering a processing grid that makes use of the SIMD (Single Instruction Multiple Data) paradigm.…”