Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Abstract

In this paper, the minimum adder-delay Discrete Cosine Transform (DCT) architecture is proposed using the Adaptive CORDIC (ACor) algorithm with fixed-rotation implementations. The proposed method has six different versions differ from the number of DCT point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S). The Altera Stratix IV and Stratix II FPGAs were used to built and verified the implementations. The 2S designs of 8p, 16p, and 32p DCT achieved the timing performances of four, five, and six adder-delay results, respectively. The proposed method was proven to have the best timing performances, good accuracy results, and adequate resources cost in comparison with other recent works.

A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

“…The reason is that the proposed EARC_2 is implemented by the cooperation between EARC and the conventional CORDIC to overcome the rotation angle out of the convergence range of EARC, and the scale factor of the conventional CORDIC is combined with the post scale factor in DCT/IDCT, which is realized by the enhanced radix-2 scale factor approximation. In the meantime, we also use the MSE mentioned in [21] to compare our proposed algorithm with the ones described in [21]. As illustrated in [21], the MSE of the 2S-8P-DCT and 3S-8P-DCT are 1.403e-4 and 3.864e-5, individually, and the MSE of our proposed unified DCT/IDCT architecture is 9.462e-7, which is much less than 2S-8P-DCT and 3S-8P-DCT.…”

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC

“…The fixed-rotation ACor happened when the input angle of z 0 is known. Fixed-rotation ACor implementations were common in CORDIC-based DCT SFGs [14,15,24]. With the known z 0 -value, the iteration process of the z j becomes a pre-determination process.…”

“…As proven in 2018 [24], when comparing the two ACor settings of 2S and 3S, the 3S-ACor-based 32-point DCT (3S-32p-DCT) had a little advantage in precision, but the cost of adder-delay and number of adders had made the trade-off not worthed. Therefore, the 2S-ACor of 32-point DCT (2S-32p-DCT) was the best design for further implementation.…”

“…Later, various improvements of the ACor implementation had been developed through the years [19,20,21,22]. The latest improvement of the ACor was the work of Hong-Thu Nguyen et al in 2015 [23], and the DCT implementation that based on it was also introduced in 2018 [24].…”

“…In this paper, the measurement result of the 65-nm Silicon On Thin Buried-oxide (SOTB) chip of the 32-point DCT architecture based on Adaptive CORDIC (ACor) is presented. The ACor-based DCT architecture was proposed in the previous work [24] in 2018, and it was proved to have the minimum adder-delay while providing good accuracy outcomes with a similar resources cost in comparison with other works. The SOTB process was chosen because it is on the development trend of low-power Complementary Metal Oxide Semiconductor (CMOS) device; the prominent advantage of the SOTB process was the ultra-low-power aspect [25,26].…”