Minimizing power supply noise through harmonic mappings in networks-on-chip

Dahir, Nizar; Mak, Terrence; Xia, Fei; Yakovlev, Alex

doi:10.1145/2380445.2380468

Cited by 9 publications

(9 citation statements)

References 26 publications

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“…Moreover, to test the proposed architecture on real application benchmarks, we adopted three different size tests used in [41]. These benchmarks are mapped to NoC platforms with the aim of reducing the overall communication energy.…”

Section: System Level Evaluation and Discussionmentioning

confidence: 99%

Hybrid wire‐surface wave interconnects for next‐generation networks‐on‐chip

Karkar

Turner²,

Tong

et al. 2013

IET Computers & Digital Techniques

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Networks-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal-based NoC pursuit offers limited scalability with the relentless technology scaling especially in global communications. To meet the scalability demand, this study proposes a new hybrid architecture empowered by both metal interconnect and Zenneck surface waves interconnects (SWIs). This architecture reduces the NoC average hop count between any communication pairs, which has been reflected as a better average delay and throughput. Furthermore, SWI enables more efficient power dissipation and faster cross the chip signal propagation. The authors' initial results based on a cycle-accurate simulator demonstrate the effectiveness of the proposed system architecture, such as significant power reduction (23%), large average delay reduction (34%) and higher throughput (35%) compared with regular NoC. These results are achieved with negligible hardware and area overhead. This study explores promising potentials of SWI for future complex global communication.

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Section: System Level Evaluation and Discussionmentioning

confidence: 99%

Hybrid wire‐surface wave interconnects for next‐generation networks‐on‐chip

Karkar

Turner²,

Tong

et al. 2013

IET Computers & Digital Techniques

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“…-Monitoring progress in transactions (link level failures, deadlock detection) [11,12], -Power noise and thermal monitoring [13], -Non-blocking communications [14].…”

Section: • Mechanisms In Communication Fabricmentioning

confidence: 99%

“…In this paper we restrict ourselves by discussing only the first category of mechanisms. An interested reader may find the description of mechanisms in the second category in our papers [11][12][13][14][15]. Our main focus here in on self-awareness, hence sensing is our priority.…”

Section: • Mechanisms In Communication Fabricmentioning

confidence: 99%

Enabling Survival Instincts in Electronic Systems: An Energy Perspective

Yakovlev¹

2015

Transforming Reconfigurable Systems

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The writing of this paper has been inspired by the motivating ideas of incorporating self-awareness into systems that have been studied by Prof Cheung in connection to dealing with variability and ageing in nano-scale electronics. We attempt here to exploit the opportunities for making systems self-aware, and taking it further, see them in a biological perspective of survival under harsh operating conditions. Survivability is developed here in the context of the availability of energy and power, where the notion of power-modulation will navigate us towards the incorporation into system design of the mechanisms analogous to instincts in human brain. These mechanisms are considered here through a set of novel techniques for reference-free sensing and elastic memory for data retention. This is only a beginning in the exploration of system design for survival, and many other developments such as design of self-aware communication fabric are further on the way.

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“…These benchmarks include a generic complex multimedia system (MMS) which comprises an h263 video encoder and an mp3 audio decoder [Hu and Marculescu 2003], a telecommunication benchmark (TELE) [Murali and De Micheli 2004], and the AMI49 and AMI25 scenarios which originally extracted from the Microelectronics Center of North Carolina benchmark suite and are found in Ababei et al [2011]. Mapping these applications to different-size NoC is archived using the algorithm proposed in Dahir et al [2012]. However, these benchmarks are small to evaluate in a 3D NoC platform (the biggest is AMI49 which consist of 49 tasks).…”

Section: Real Application Benchmarksmentioning

confidence: 99%

Dynamic programming-based runtime thermal management (DPRTM)

Al-Dujaily

Dahir

Mak

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Complex thermal behavior inhibits the advancement of three-dimensional (3D) very-large-scale-integration (VLSI) system designs, as it could lead to ultra-high temperature hotspots and permanent silicon device damage. This article introduces a new runtime thermal management strategy to effectively diffuse and manage heat throughout 3D chip geometry for a better throughput performance in networks on chip (NoC). This strategy employs a dynamic programming-based runtime thermal management (DPRTM) policy to provide online thermal regulation. Reactive and proactive adaptive schemes are integrated to optimize the routing pathways depending on the critical temperature thresholds and traffic developments. Also, when the critical system thermal limit is violated, an urgent throttling will take place. The proposed DPRTM is rigorously evaluated through cycle-accurate simulations, and results show that the proposed approach outperforms conventional approaches in terms of computational efficiency and thermal stability. For example, the system throughput using the DPRTM approach can be improved by 33% when compared to other adaptive routing strategies for a given thermal constraint. Moreover, the DPRTM implementation presented in this article demonstrates that the hardware overhead is insignificant. This work opens a new avenue for exploring the on-chip adaptability and thermal regulation for future large-scale and 3D many-core integrations.

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Minimizing power supply noise through harmonic mappings in networks-on-chip

Cited by 9 publications

References 26 publications

Hybrid wire‐surface wave interconnects for next‐generation networks‐on‐chip

Hybrid wire‐surface wave interconnects for next‐generation networks‐on‐chip

Enabling Survival Instincts in Electronic Systems: An Energy Perspective

Dynamic programming-based runtime thermal management (DPRTM)

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