Minimization of power consumption of finite state machines by splitting their internal states

Grzes, Tomasz; Соловьев, В. В.

doi:10.1134/s1064230715030090

Cited by 12 publications

(11 citation statements)

References 16 publications

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“…The state splitting procedure may lead to a decrease in power dissipation of the FSM [7] and to a gain in its speed of operation [40]. Any splitting of states leads to a growth in the number of states and hence, may lead to an increase in the number of memory elements needed for FSM implementation (increasing the cost).…”

Section: State Splitting Proceduresmentioning

confidence: 99%

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State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Klimowicz

Salauyou

2022

Applied Sciences

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Different strategies for the combination of merging and splitting transformation procedures for incompletely specified finite state machines implemented on field-programmable logic devices are offered. In these methods, such optimization criteria as the speed of operation, power consumption and implementation cost are considered already in the early phase of finite state machine synthesis. The methods also take into account the technological features of programmable logic devices and the state assignment method. The transformation quality ratio is calculated on the base of estimations of consumed power, critical path delay and number of utilized logic cells. The user is also able to choose the order of merging and splitting procedures and the direction of the optimization by setting weights for each criterion. The methods of the estimation of optimization criteria values are described, and the experimental results are also discussed.

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Section: State Splitting Proceduresmentioning

confidence: 99%

“…The value of splitting the states of FSMs in state encoding procedure was declared in [6] and soon after in [7], where the splitting operation was used to decrease the power dissipation and resource utilization of the designed FSM. Ref.…”

Section: Introductionmentioning

confidence: 99%

State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Klimowicz

Salauyou

2022

Applied Sciences

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“…, }, descriptions of two FSMs, that is, base ckt and recon ckt b, are taken as inputs. The major contributing factors for power consumption and LUT requirement in FSM are the number of inputs and the internal states [8,19]. In any FSM, input variable and states are interdependent.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…In FSM, splitting a state with high transitions results in low power consumption [8,19]. It also improves the operating speed [2,20].…”

Section: Proposition 1 Dummy Transitions In a Matched State Of Base mentioning

confidence: 99%

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FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Das

Priya

2018

International Journal of Reconfigurable Computing

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The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

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Combined State Merging and Splitting Procedure for Low Power Implementations of Finite State Machines

Klimowicz

Grzes

2021

Advances in Systems Engineering

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Minimization of power consumption of finite state machines by splitting their internal states

Cited by 12 publications

References 16 publications

State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Combined State Merging and Splitting Procedure for Low Power Implementations of Finite State Machines

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